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Two input-two output differential latch circuit

  • US 5,625,308 A
  • Filed: 11/14/1995
  • Issued: 04/29/1997
  • Est. Priority Date: 06/08/1995
  • Status: Expired due to Term
First Claim
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1. A differential latch circuit comprising:

  • a first load resistor having a first terminal coupled to a first power supply terminal, and a second terminal coupled to a first node;

    a second load resistor having a first terminal coupled to said first power supply terminal, and a second terminal coupled to a second node;

    a first transistor having a first electrode, a second electrode, and a control electrode coupled to a first input terminal;

    a second transistor having a first electrode, a second electrode, and a control electrode coupled to a second input terminal;

    a constant current source having a first terminal directly connected to the second electrodes of said first and second transistors, and a second terminal directly connected to a second power supply terminal;

    a latch circuit receiving signals from said first and second nodes for generating two complementary logic signals from the voltages of the received signals to output the two complementary logic signals from first and second output terminals;

    a first switch circuit for simultaneously controlling current conduction and non-conduction between said first node and said first transistor and between said second node and said second transistor; and

    a second switch circuit for operating the latch circuit in a through mode in which signals at said first and second nodes amplified by said first and second transistors are output from said first and second output terminals, respectively, when said first switch circuit is in a current conduction mode and for operating said latch circuit in a latch mode to latch signals existing at said first and second modes when said first switch circuit is in a current non-conduction mode.

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