Method and apparatus for interleaving display buffers

• US 5,625,386 A
• Filed: 09/30/1994
• Issued: 04/29/1997
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: Apple Computer Incorporated (Apple Inc.)
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Bailey, Robert L., Howard, Brian D.
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): CHANG, KENT WU
• Application Number:
  US08/315,653
• Time in Patent Office: 942 Days
• Field of Search: 345/1, 345/3, 345/201, 345/98, 345/203, 345/196, 345/200, 345/185, 345/189, 395/165, 395/164
• US Class Current: 345/540
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence

Abstract

A method and an apparatus for interleaving display frame buffers is disclosed. The system includes a processor providing CPU addresses for peripheral access, a display system, a single memory system for storing multiple frame buffers, data buses for transferring image information and a video controller for processing the image information received and for converting CPU addresses into memory addresses for accessing the memory system. The multiple frame buffers stored in the memory system in accordance with the present invention provide either overlay images for a display or separate images for separate displays or both.

Claims

1. A computer system including a processor and a display system, said display system comprises:

a display means for displaying images;

a video bus having a sequence of T-bit data words for carrying image information;

a first logical frame buffer and a second logical frame buffer containing the image information and the image information from each frame buffer is carried in separate T-bit data words and both frame buffers having P₁ bits per pixel and P₂ bits per pixel respectively where

1) P₂ /P₁ =n, and n is a number ranging from 1 to T;

2) T≧

P₁ and T≧

P₂ ;

3) X₁ and X₂ being integers and are numbers of pixels separately stored in each T-bit data word for the first logical frame buffer and the second logical frame buffer respectively, X₁ ranging from 1 to TRUNCATE (T/P₁) and X₂ ranging from 1 to TRUNCATE (T/P₂); and

4) the sequence of the T-bit data words carrying the image information in a repeating pattern such that for each X₁ pixels of the first frame buffer carried there is an immediate corresponding X₁ pixels of the second frame buffer also being carried by the sequence so that the pattern repeats itself after every 2X₁ pixels;

a memory system of sufficient size for storing the image information as represented by both logical frame buffers, the memory system being coupled to the video bus for transferring the image information, the memory system is arranged such that the two logical frame buffers are stored therein for the simultaneous transfer of the image information from each frame buffer according to a data clock rate; and

a video display controller being coupled to the display means and to the video bus for receiving the image information and for processing the image information for use by said display means.

2. The computer system of claim 1 wherein the memory system is further coupled to the processor via a system bus.

3. The computer system of claim 1 wherein the video display controller is coupled to the processor and further includes an address generator for receiving CPU addresses from the processor and for responsively generating memory addresses for accessing the memory system, the address generator converting each CPU address into its memory address counterpart according the following formulae:

For accessing the first logical frame buffer;

space="preserve" listing-type="equation">memory address=CPU address+n (CPU address)

For accessing the second logical frame buffer;

space="preserve" listing-type="equation">memory address=CPU address+(CPU address DIV n)+1

where address DIV n is equivalent to shifting the address right y bit positions, where 2^y =n, which removes y least significant bits from the address.

4. The computer system of claim 1 wherein the video display controller is coupled to the processor and further includes an address generator for receiving CPU addresses from the processor and for responsively generating memory addresses for accessing the memory system, the address generator converting each CPU address into its memory address counterpart according the following formulae:

For accessing the first logical frame buffer;

space="preserve" listing-type="equation">memory address=CPU address+n (CPU address)+n

For accessing the second logical frame buffer;

space="preserve" listing-type="equation">memory address=CPU address+(CPU address DIV n)

where address DIV n is equivalent to shifting the address right y bit positions, where 2^y =n, which removes y least significant bits from the address.

5. The computer system of claim 1 wherein the video display controller is coupled to the processor and further includes an address generator for receiving CPU addresses from the processor and for responsively generating memory addresses including R bits of row address and C bits of column address for accessing the memory system, the CPU addresses including column and row address portions, the address generator leaving the row address portion of the CPU addresses unchanged as the row portion of the memory address and converting column portion of the CPU addresses into their memory address counterparts according the following formulae:

space="preserve" listing-type="tabular">______________________________________ For accessing the first logical frame buffer;

memory column address = C LSB'"'"'s of {CPU column address + n (CPU column address)}; and

For accessing the second logical frame buffer;

memory column address = C LSB'"'"'s of {CPU column address + (CPU column address DIV n) + 1};

______________________________________

where LSB represents least significant bit and where address DIV n is equivalent to shifting the address right y bit positions, where 2^y =n, which removes y least significant bits from the address.

6. The computer system of claim 1 wherein said display means includes two displays and wherein said video display controller separates said two logical frame buffers into two separate data streams and directs the data streams individually and separately to the two displays.

7. The computer system of claim 1 wherein said video display controller determines the image information from which frame buffer is to be applied to a specific pixel location on said display means.

8. The computer system of claim 1 wherein said memory system includes DRAM.

9. The computer system of claim 1 wherein said memory system includes VRAM.

10. An expansion card for video display control removably attached to a computer system that has a processor and a display means for displaying images, said expansion card comprises:

a video bus having a sequence of T-bit data words for carrying image information;

a first logical frame buffer and a second logical frame buffer containing the image information and the image information from each frame buffer is carried in separate T-bit data words and both frame buffers having P₁ bits per pixel and P₂ bits per pixel respectively where

1) P₂ /P₁ =n, and n is a number ranging from 1 to T;

2) T≧

P₁ and T≧

P₂ ;

3) X₁ and X₂ being integers and are numbers of pixels separately stored in each T-bit data word for the first logical frame buffer and the second logical frame buffer respectively, X₁ ranging from 1 to TRUNCATE (T/P₁) and X₂ ranging from 1 to TRUNCATE (T/P₂); and

4) the sequence of the T-bit data words carrying the image information in a repeating pattern such that for each X₁ pixels of the first frame buffer carried there is an immediate corresponding X₁ pixels of the second frame buffer also being carried by the sequence so that the pattern repeats itself after every 2X₁ pixels;

a memory system of sufficient size for storing the image information as represented by both logical frame buffers, the memory system being coupled to the video bus for transferring the image information, the memory system is arranged such that the two logical frame buffers are stored therein for the simultaneous transfer of the image information from each frame buffer according to a data clock rate; and

a video display controller being coupled to the display means and to the video bus for receiving the image information and for processing the image information for use by said display means.

11. The expansion card of claim 10 wherein the memory system is further coupled to the processor via a system bus.

12. The expansion card of claim 10 wherein the video display controller is coupled to the processor and further includes an address generator for receiving CPU addresses from the processor and for responsively generating memory addresses for accessing the memory system, the address generator converting each CPU address into its memory address counterpart according the following formulae:

For accessing the first logical frame buffer;

space="preserve" listing-type="equation">memory address=CPU address+n (CPU address)

For accessing the second logical frame buffer;

space="preserve" listing-type="equation">memory address=CPU address+(CPU address DIV n)+1

where address DIV n is equivalent to shifting the address right y bit positions, where 2^y =n, which removes y least significant bits from the address.

13. The expansion card of claim 10 wherein the video display controller is coupled to the processor and further includes an address generator for receiving CPU addresses from the processor and for responsively generating memory addresses for accessing the memory system, the address generator converting each CPU address into its memory address counterpart according the following formulae:

For accessing the first logical frame buffer;

space="preserve" listing-type="equation">memory address=CPU address+n (CPU address)+n

For accessing the second logical frame buffer;

space="preserve" listing-type="equation">memory address=CPU address+(CPU address DIV n)

where address DIV n is equivalent to shifting the address right y bit positions, where 2^y =n, which removes y least significant bits from the address.

14. The expansion card of claim 10 wherein the video display controller is coupled to the processor and further includes an address generator for receiving CPU addresses from the processor and for responsively generating memory addresses including R bits of row address and C bits of column address for accessing the memory system, the CPU addresses including column and row address portions, the address generator leaving the row address portion of the CPU addresses unchanged as the row portion of the memory address and converting column portion of the CPU addresses into their memory address counterparts according the following formulae:

For accessing the first logical frame buffer;

space="preserve" listing-type="equation">memory column address=C LSB'"'"'s of {CPU column address+n (CPU column address)}; and

For accessing the second logical frame buffer;

space="preserve" listing-type="equation">memory column address=C LSB'"'"'s of {CPU column address+(CPU column address DIV n)+1};

where LSB represents least significant bit and where address DIV n is equivalent to shifting the address right y bit positions, where 2^y =n, which removes y least significant bits from the address.

15. The expansion card of claim 10 wherein said display means includes two displays and wherein said video display controller separates said two logical frame buffers into two separate data streams and directs the data streams individually and separately to the two displays.

16. The expansion card of claim 10 wherein said video display controller determines the image information from which frame buffer is to be applied to a specific pixel location on said display means.

17. The expansion card of claim 10 wherein said memory system includes DRAM.

18. The expansion card of claim 10 wherein said memory system includes VRAM.