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Method and apparatus for compacting integrated circuits with standard cell architectures

  • US 5,625,568 A
  • Filed: 09/27/1994
  • Issued: 04/29/1997
  • Est. Priority Date: 12/22/1993
  • Status: Expired due to Fees
First Claim
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1. A method for compacting an integrated circuit layout that includes a plurality of standard cells, the method being executed by a processor having a memory and controlled by a program stored in the memory, the method including the steps of:

  • (1) storing in said memory a connectivity data structure representing the integrated circuit layout as a set of cells, each said cell being defined as a given material or as empty, the data structure including data representing points defining edges and boundaries of said cells, the data structure further including connector cell data fields to identify whether each cell forms a portion of a connected group of cells;

    (2) compacting said integrated circuit layout in accordance with a predetermined criteria to obtain a compacted integrated circuit layout; and

    (3) re-organizing said compacted integrated circuit layout in accordance with predetermined standard cell design criteria.

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