Method and apparatus for compacting integrated circuits with standard cell architectures

• US 5,625,568 A
• Filed: 09/27/1994
• Issued: 04/29/1997
• Est. Priority Date: 12/22/1993
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Ngo, Andy T., Edwards, Lawrence B.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US08/313,706
• Time in Patent Office: 945 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 371/61, 368/113, 424/70.12
• US Class Current: 716/122
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A computer-aided design system for compacting an integrated circuit layout with standard cell components is described. A data receiving device is used to process an integrated circuit layout that includes standard cell components. The integrated circuit layout is characterized by a circuit layout database with a cell table defining a set of cells that represent all spaces in the integrated circuit layout. The cell table includes connector cell data to indicate whether a cell forms a portion of a connected group of cells. The system includes an adjustment mechanism to align internal connectors of a standard cell with a routing grid associated with the integrated circuit layout. The system also includes a movement mechanism to position right-edge external connectors of a standard cell at a uniform routing grid coordinate position. The system uses the connector cell data to identify a power bus and a ground bus of each standard cell. Thereafter, a minimum edge to edge distance is assigned to each power bus and each ground bus. The connector cell data is also used to identify second metal plane routing paths. The system repositions selected second metal plane routing paths to increase routing path options.

Claims

1. A method for compacting an integrated circuit layout that includes a plurality of standard cells, the method being executed by a processor having a memory and controlled by a program stored in the memory, the method including the steps of:

(1) storing in said memory a connectivity data structure representing the integrated circuit layout as a set of cells, each said cell being defined as a given material or as empty, the data structure including data representing points defining edges and boundaries of said cells, the data structure further including connector cell data fields to identify whether each cell forms a portion of a connected group of cells;

(2) compacting said integrated circuit layout in accordance with a predetermined criteria to obtain a compacted integrated circuit layout; and

(3) re-organizing said compacted integrated circuit layout in accordance with predetermined standard cell design criteria.

2. The method of claim 1 wherein said re-organizing step includes the step of adjusting internal connectors of each standard cell such that each internal connector corresponds to a routing grid associated with said integrated circuit layout.

3. The method of claim 2 wherein said re-organizing step includes the step of moving right-edge external connectors of a standard cell to a uniform position.

4. The method of claim 2 wherein said re-organizing step includes the steps of:

using said connector cell data fields to identify a power bus and a ground bus for each of said standard cells; and

assigning a minimum edge to edge distance for said power bus and said ground bus.

5. The method of claim 2 wherein said re-organizing step includes the steps of:

using said connector cell data fields to identify second metal plane routing paths; and

repositioning selected second metal plane routing paths to increase routing path options.

6. A computer readable memory that can be used to direct a computer to function in a specified manner, comprising:

a connectivity data structure to represent an integrated circuit layout as a set of cells, each said cell being defined as a given material or as empty, the data structure including data fields representing points defining edges and boundaries of said cells, the data structure further including connector cell data fields to identify whether each cell forms a portion of a connected group of cells; and

executable instructions stored in said memory, said executable instructions including;

a first set of instructions to compact said integrated circuit layout in accordance with a predetermined criteria to obtain a compacted integrated circuit layout, and

a second set of instructions to re-organize said compacted integrated circuit layout in accordance with predetermined standard cell design criteria.

7. The apparatus of claim 6 wherein said second set of instructions includes instructions to adjust internal connectors of each standard cell such that each internal connector corresponds to a routing grid associated with said integrated circuit layout.

8. The apparatus of claim 6 wherein said second set of instructions includes instructions to move right-edge external connectors of a standard cell to a uniform position.

9. The apparatus of claim 6 wherein said second set of instructions includes:

instructions to use said connector cell data fields to identify a power bus and a ground bus for each of said standard cells; and

instructions to assign a minimum edge to edge distance for said power bus and said ground bus.

10. The apparatus of claim 6 wherein said second set of instructions includes:

instructions to use said connector cell data fields to identify second metal plane routing paths; and

instructions to reposition selected second metal plane routing paths to increase routing path options.