Hardware modeling system and method of use

• US 5,625,580 A
• Filed: 09/26/1994
• Issued: 04/29/1997
• Est. Priority Date: 05/31/1989
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Kappauf, William F., Scheffer, Louis K., Widdoes, Lawrence C. Jr., Heideman, Wayne P., Read, Andrew J., Mardjuki, Robert K., Couch, Robert K., Jaeger, Peter R., Papamarcos, Mark S.
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/313,529
• Time in Patent Office: 946 Days
• Field of Search: 364/578, 364/579, 364/488, 364/490, 371/27, 371/29.1, 324/73.1, 324/158 R, 395/183.07, 395/183.08
• US Class Current: 703/21
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimulus pattern sequences, pin electronics circuitry which is used for driving the pattern sequences on the pattern bus to the hardware modeling element and then sensing the five state values of the hardware modeling element pins, and an adapter that is used for fixturing the hardware modeling element to the pin electronics circuitry with the adapter supporting live insertion into a powered hardware modeling system.

Claims

1. A hardware modeling system adapted for coupling to one of a predetermined collection of host computers, the hardware modeling system for evaluating a response of an electronic device or circuitry to stimulation from the hardware modeling system, with pins of the electronic device or circuitry being electrically coupled to pin drivers of the hardware modeling system, comprising:

a. a host connection means configured for coupling a host computer for transmitting bi-directionally thereon communications between the hardware modeling system and a host computer;

b. microprocessor means coupled to the host connection means for controlling programmed operation of the hardware modeling system;

c. central timing control means for generating timing signals for controlling timing of operations of the hardware modeling system, the central timing control means coupled to the microprocessor means and a pattern bus means for generating sample strobes for sampling outputs of the pins of the electronic device or circuitry and edge strobes for formatting stimulation patterns;

d. pattern bus means coupled to the central timing control means and the microprocessor, the pattern bus means having a first mode of operation for the microprocessor means to access certain circuitry for conducting read and write operations and a second mode of operation for presenting the stimulation patterns to the pins of the electronic device or circuitry which is electrically coupled to the hardware modeling system;

e. pattern controller means coupled to the pattern bus means for controlling stimulation pattern sequencing and delivery of stimulation patterns to the pattern bus;

f. pattern memory means coupled to the pattern controller means for storing the stimulation patterns in the pattern memory means in a plurality of memory means bits;

g. pin electronics circuitry coupled to the pattern bus means for driving and sensing the pins of the electronic device or circuitry, and the pin electronics circuitry providing sensing of at least four states of the pins of electronic device or circuitry; and

h. adaptor means coupled to the pin electronics circuitry and the pins of the electronic device or circuitry, the adaptor means configured for electrically receiving the electronic device or circuitry wherein the adaptor means includes circuitry for supporting live-insertion into a powered hardware modeling system.

2. A method of communicating between a networked hardware modeling system and one of a plurality of simulators running on one of a plurality of computers coupled to the network, comprising the steps of communicating in a simulator-independent manner and responding concurrently.

3. A method of testing the functionality of an electronic device or circuitry electrically coupled to pin electronics circuitry of a hardware modeling system, comprising the steps of:

a. reading a test vector from a storage device;

b. stimulating the electronic device or circuitry with the pin electronics circuitry according to the test vector;

c. measuring a response by the electronic device or circuitry to the step of stimulating, thereby forming a measured response; and

d. comparing the measured response to a stored predetermined response to determine if the electronic device or circuitry is functional.

4. The method as recited in claim 3, wherein the hardware modeling system has a plurality of electronic devices or circuits coupled thereto with each electronic device or circuitry having at least one pin that is electrically coupled to the pin electronics circuitry of the hardware modeling system.

5. A method of executing hardware diagnostics for a networked hardware modeling system, comprising the steps of controlling execution of the diagnostics remotely from one of a plurality of computers coupled to the network and concurrently transmitting the status of the hardware modeling system to one of the plurality of computers.

6. A hardware modeling system for stimulating and sensing a response of electronic devices or circuitry to a stimulus, the hardware modeling system configured for coupling to a plurality of electronic devices or circuitry and comprising a plurality of interfaces each having pin electronics circuitry for driving and sensing low-voltage CMOS electronic devices or circuitry operating at a supply voltage of 3.3 V.

7. A method of configuring a width of memory in a hardware modeling system, wherein the memory is used to store a stimulation pattern sequence for presentation in parallel to pins of an electronic device or circuitry, comprising the steps of coupling a variable number of memory devices in parallel to a pattern bus and storing a stimulation pattern therein.

8. The method as recited in claim 7, wherein the width of the memory is configured up to a size for supporting 320-pin electronic devices or circuitry.

9. A hardware modeling system adapted for coupling to one of a predetermined collection of host computers, the hardware modeling system evaluating a response of an electronic device or circuitry to stimulation from the hardware modeling system, with pins of the electronic device or circuitry being electrically coupled to pin drivers of the hardware modeling system, comprising:

a. a host network configured for coupling to a host computer for transmitting bi-directionally thereon communications between the hardware modeling system and the host computer;

b. microprocessor circuitry coupled to the host network for coupling programmed operation of the hardware modeling system;

c. central timing controller for generating timing signals for controlling timing of operations of the hardware modeling system, the central timing controller coupled to the microprocessor circuitry and a pattern bus for generating sample strobes for sampling outputs of the pins of the electronic device or circuitry and edge strobes for formatting stimulation patterns;

d. pattern bus coupled to the microprocessor and the central timing controller, the pattern bus having a first mode of operation wherein the pattern bus allows the microprocessor circuitry to access certain circuitry for conducting read and write operations and a second mode of operation wherein the pattern bus presents the stimulation patterns to the pins of the electronic device or circuitry which is electrically coupled to the hardware modeling system;

e. pattern controller coupled to the pattern bus for controlling stimulation pattern sequencing and delivery of stimulation patterns to the pattern bus;

f. pattern memory device coupled to the pattern controller for storing the stimulation patterns in the pattern memory device in a plurality of memory bits;

g. pin electronics circuitry coupled to the pattern bus for driving and sensing the pins of the electronic device or circuitry, and the pin electronics circuitry providing sensing of at least four states of the pins of the electronic device or circuitry; and

h. an adaptor coupled to the pin electronics circuitry and configured for coupling the electronic device or circuitry to the hardware modeling system, the adaptor having circuitry for supporting live-insertion into a powered hardware modeling system.

10. A hardware modeling system for stimulating and sensing a response of electronic devices or circuitry to a stimulus, the hardware modeling system coupled to a plurality of electronic devices or circuitry, wherein pin electronics circuitry of the hardware modeling system drives and senses low-voltage CMOS electronic devices or circuitry operating at a supply voltage of 3.3 V.

11. A hardware modeling system for evaluating a response of an electronic device or circuitry to a stimulation pattern received from the hardware modeling system, with pins of the electronic device or circuitry being electrically coupled to pin drivers of the hardware modeling system, comprising:

a. a host network configured for coupling to a host computer for transmitting bi-directional communications between the hardware modeling system and the host computer;

b. a microprocessor coupled for controlling the hardware modeling system;

c. a central timing controller coupled to the microprocessor for generating timing signals for controlling timing of operations of the hardware modeling system, the central timing controller for generating sample strobes for sampling the outputs of the pins of the electronic device or circuitry and generating edge strobes for formatting the stimulation patterns;

d. a pattern bus coupled to the central timing controller and the microprocessor, the pattern bus having a first mode of operation wherein the pattern bus allows the microprocessor to access certain circuitry for conducting read and write operations and a second mode of operation wherein the pattern bus is utilized to present the stimulation patterns to the pins of the electronic device or circuitry which is electrically coupled to the hardware modeling system;

e. a pattern controller coupled to the pattern bus for controlling stimulation pattern sequencing and delivery of stimulation patterns to the pattern bus;

f. a pattern memory device coupled to the pattern controller for storing the stimulation patterns in the pattern memory device in a plurality of memory bits;

g. pin electronics circuitry coupled to the pattern bus for driving and sensing the pins of the electronic device or circuitry, and the pin electronics circuitry providing sensing of at least four states of the pins of the electronic device or circuitry; and

h. an adaptor coupled to the pin electronics circuitry and configured for coupling the electronic device or circuitry to the hardware modeling system, the adaptor having circuitry for supporting live-insertion into a powered hardware modeling system.

12. A hardware modeling system for evaluating an electronic device or circuitry by generating a stimulation pattern, coupling the stimulation pattern to the electronic device or circuitry and sensing a response therefrom, the electronic device or circuitry having a plurality of electrical contacts, and further wherein the hardware modeling system is adapted to be coupled for bi-directional communications to a host network, the hardware modeling system comprising:

a. a central processing unit (CPU) coupled for controlling the hardware modeling system;

b. a central timing controller coupled to receive control signals from the CPU for generating timing signals for controlling timing of operations of the hardware modeling system, the central timing controller for generating sample strobes for sampling outputs of the electronic device or circuitry and generating edge strobes for exercising the electronic device or circuitry, the central timing controller also coupled to provide the response to the host network;

c. a pattern bus coupled to the central timing controller and the microprocessor, the pattern bus having a first mode of operation wherein the pattern bus allows the microprocessor to access certain circuitry for conducting read and write operations and a second mode of operation wherein the pattern bus is utilized to present the stimulation patterns to the pins of the electronic device or circuitry which is electrically coupled to the hardware modeling system;

d. a pattern generator including;

(1) a pattern memory device for storing the stimulation pattern; and

(2) a pattern controller coupled for control by the central timing controller for retrieving the stimulation pattern and providing the stimulation pattern to the bus according to the edge strobes; and

e. an interface circuit bi-directionally coupled to receive the stimulation pattern from the bus for providing the stimulation pattern to the electronic device or circuitry and for sensing signals applied by the electronic device or circuitry to the contacts.

13. The hardware modeling system according to claim 12, further comprising an adaptor coupled to the interface circuit for supporting live-insertion of the electronic device or circuitry into a powered hardware modeling system.

14. The hardware modeling system according to claim 12, wherein the bus has a first mode of operation for the CPU to access certain circuitry for conducting read and write operations and a second mode of operation for presenting the stimulation patterns to the contacts of the electronic device or circuitry.

15. The hardware modeling system according to claim 12, further adapted to be one of a plurality of concurrently accessible networked hardware modeling systems coupled to an electronic device or circuity for concurrent access by a networked host computer.

16. The hardware modeling system according to claim 12, wherein the interface circuit has specific circuitry associated with individual pins of the electronic device or circuitry for determining whether a selected pin is in a driving low state, driving high state, or non-driving state.

17. The hardware modeling system according to claim 12, wherein the interface circuitry drives and senses low-voltage CMOS electronic devices or circuitry operating at a supply voltage of 3.3 V.

18. The hardware modeling system according to claim 12, wherein the interface circuit drives and senses the contacts of the electronic device or circuitry and provides sensing of at least four states of the contacts.

19. The hardware modeling system according to claim 17, wherein the interface circuitry has specific circuitry associated with individual pins of the electronic device or circuitry for the voltage of a selected pin to be independently programmed, and at the same time, automatically compare the voltage of the pin with at least two reference voltages.

20. The hardware modeling system according to claim 17, wherein the interface circuitry has specific circuitry associated with individual pins of the electronic device or circuitry for the voltage of a selected pin to be independently programmed, and at the same time, automatically compare the current into the pin with at least two reference currents.