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Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit

  • US 5,625,592 A
  • Filed: 05/23/1996
  • Issued: 04/29/1997
  • Est. Priority Date: 11/20/1995
  • Status: Expired
First Claim
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1. A method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate, said method comprising:

  • a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out; and

    b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, said second period being shorter than the first period.

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