Method and circuit for shortcircuiting data transfer lines and semiconductor memory device having the circuit

• US 5,625,592 A
• Filed: 05/23/1996
• Issued: 04/29/1997
• Est. Priority Date: 11/20/1995
• Status: Expired

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Shinozaki, Naoharu
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/657,484
• Time in Patent Office: 341 Days
• Field of Search: 365/189.01, 365/190, 365/203, 365/204
• US Class Current: 365/189.14
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

There is provided a method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate. The method includes a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out, and b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, the second period being shorter than the first period.

Claims

1. A method of controlling data transmission lines of a semiconductor memory device which has a first pair of data transmission lines to which a sense amplifier and memory cells are connected, and a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate, said method comprising:

a) shortcircuiting the second pair of data transmission lines for a first period when a read operation is carried out; and

b) shortcircuiting the second pair of data transmission lines for a second period when a write operation is carried out, said second period being shorter than the first period.

2. A semiconductor device comprising:

memory cells;

a sense amplifier;

a first pair of data transmission lines to which the sense amplifier and memory cells are connected;

a second pair of data transmission lines to which a read circuit and a write circuit are connected at an end of the second pair of the data transmission lines, which is connected to the first pair of data transmission lines via a column gate;

a shortcircuiting element which can shortcircuit the second pair of data transmission lines; and

a first control circuit which controls the shortcircuiting element so that the second pair of data transmission lines is shortcircuited for a first period when a read operation is carried out, and the second pair of data transmission lines is shortcircuited for a second period when a write operation is carried out, said second period being shorter than the first period.

3. The semiconductor memory device as claimed in claim 2, wherein the second pair of data transmission lines comprises:

a third pair of data transmission lines to which the first pair of data transmission lines is connected; and

a fourth pair of data transmission lines to which the read circuit and the write circuit are connected, the fourth pair of data transmission lines being coupled to the third pair of data transmission lines via a switch circuit.

4. The semiconductor memory device as claimed in claim 2, further comprising a precharging circuit which supplies a precharge voltage to the second pair of data transmission lines.

5. The semiconductor memory device as claimed in claim 4, wherein said precharging circuit supplies the precharge voltage to the second pair of data transmission lines while the second pair of data transmission lines is being shortcircuited, and does not supply the precharge voltage thereto when the second pair of data transmission lines is not shortcircuited.

6. The semiconductor memory device as claimed in claim 2, wherein the first control circuit controls the shortcircuiting element so that a timing at which the second pair of data transmission lines is shortcircuited substantially coincides with a first signal defining an operation timing in the read and write operations, and a timing at which the second pair of data transmission lines is released from a shortcircuited state in the write operation is earlier, with respect to the first signal, than a timing at which the second pair of data transmission lines is released from the shortcircuited state in the read operation.

7. The semiconductor memory device as claimed in claim 4, wherein the first control circuit controls the shortcircuiting element so that the second pair of data transmission lines is released from a shortcircuited state in the read operation after the second pair of data transmission lines is precharged to the precharge voltage.

8. The semiconductor memory device as claimed in claim 4, wherein the first control circuit controls the shortcircuiting element so that the second pair of data transmission lines is released from a shortcircuited state in the write operation before the second pair of data transmission lines is precharged to the precharge voltage.

9. The semiconductor memory device as claimed in claim 8, wherein said write circuit has a driving capability of setting the second pair of data transmission lines to the precharge voltage faster than the precharging circuit precharges the second pair of data transmission lines to the precharge voltage when the write circuit inverts complementary signals on the second pair of data transmission lines.

10. The semiconductor memory device as claimed in claim 2, wherein said first control circuit comprises:

a second control circuit which controls timings at which the second pair of data transmission lines is shortcircuited and released from a shortcircuited state in the write operation;

a third control circuit which controls timings at which the second pair of data transmission lines is shortcircuited and released from the shortcircuited state in the read operation; and

a fourth control circuit which controls a timing at which the shortcircuiting element shortcircuits the second pair of data transmission lines on the basis of output signals of the second and third control circuits.

11. The semiconductor memory device as claimed in claim 10, wherein:

the second control circuit comprises a first NAND circuit which performs a NAND operation on a first signal defining an operation timing and a second signal indicating whether an operation mode of the semiconductor memory device is the write operation or the read operation;

the third control circuit comprises a first delay circuit delaying the first signal, and a second NAND circuit performing a NAND operation on an output signal of the first delay circuit and the first signal; and

the fourth control circuit comprises a third NAND circuit performing a NAND operation on an output signal of the second control circuit and an output signal of the third control circuit, and a first inverting delay circuit which inverts and delays an output signal of the third NAND circuit.

12. The semiconductor memory device as claimed in claim 11, wherein the first signal is a signal synchronized with an external clock applied to the semiconductor memory device.

13. The semiconductor memory device as claimed in claim 2, further comprising a second control circuit which controls enabling of the write circuit which outputs data to the second pair of data transmission lines at almost the same time as the second pair of data transmission lines is released from a shortcircuited state.

14. The semiconductor memory device as claimed in claim 13, wherein said second control circuit controls the write circuit on the basis of a first signal defining an operation timing and a second signal indicating whether an operation mode of the semiconductor memory device is the write operation or the read operation.

15. The semiconductor memory device as claimed in claim 14, wherein said second control circuit comprises:

a first inverting circuit which inverts the first signal;

a second inverting circuit which inverts the second signal;

a first NOR circuit which performs a NOR operation on output signals of the first and second inverting circuits; and

a first delay circuit which delays an output signal of the first NOR circuit.

16. The semiconductor memory device as claimed in claim 2, further comprising a second control circuit which controls enabling of the write circuit on the basis of a first signal defining an operation timing and a second signal indicating whether an operation mode of the semiconductor memory device is the write operation or the read operation.

17. The semiconductor memory device as claimed in claim 16, wherein said second control circuit comprises:

a first inverting circuit which inverts the first signal;

a first NOR circuit which performs a NOR operation on an output signal of the first inverting circuit and the second signal; and

a first delay circuit which delays an output signal of the first NOR circuit.

18. The semiconductor memory device as claimed in claim 6, further comprising a second control circuit which delays the first signal to generate a third signal used to control timings at which the column gate is selected and released from a selected state at respective timings which are common to the read operation and the write operation.

19. The semiconductor memory device as claimed in claim 2, further comprising:

a second control circuit which controls timings at which a column is selected and released from a selected state in the read and write operations; and

a third control circuit which controls timings at which the column gate is selected and released from the selected state,

wherein the timing at which the column gate is selected in the write operation lags behind the timing at which the column gate is selected in the read operation, and the timing at which the column gate is released from the selected state in the read operation substantially coincides with the timing at which the column gate is released from the selected state in the write operation.

20. The semiconductor memory device as claimed in claim 19, wherein the second control circuit comprises:

a first inverting circuit which inverts a first signal defining an operation timing;

a first inverting delay circuit which inverts and delays an output signal of the first inverting circuit;

a first NAND circuit which performs a NAND operation on a second signal indicating whether an operation mode of the semiconductor memory device is the write operation or the read operation and an output signal of the first inverting circuit; and

a first delay circuit which delays an output signal of the first NAND circuit, and

wherein the third control circuit comprises;

a second NAND circuit which performs a NAND operation on an output signal of the first inverting delay circuit and an output signal of the first delay circuit; and

a second inverting circuit which inverts an output signal of the second NAND circuit.

21. The semiconductor memory device as claimed in claim 2, further comprising:

a second control circuit which controls timings at which a column is selected and released from a selected state in the read operation;

a third control circuit which controls timing at which a column is selected and released from the selected state in the write operation;

a fourth control circuit which generates, from output signals of the second and third control circuits, a third signal which controls timings at which the column gate is selected and released from the selected state; and

a fifth control circuit which controls the second control circuit,

wherein the timings at which the column gate is selected and released from the selected state in the write operation lag behind the timings at which the column gate is selected and released from the selected state in the read operation.

22. The semiconductor memory device as claimed in claim 21, wherein said second control circuit comprises:

a first inverting circuit which inverts a first signal defining an operation timing;

a first NAND circuit which performs a NAND operation on an output signal of the first inverting circuit and an output signal of the fifth control circuit; and

a first delay circuit which delays an output signal of the first NAND circuit,

wherein said third control circuit comprises;

a second NAND circuit which performs a NAND operation on a second signal indicating whether an operation mode of the semiconductor memory device is the write operation or the read operation and an output signal of the first inverting circuit; and

a second delay circuit which delays an output signal of the second NAND circuit,

wherein said fourth control circuit comprises;

a third NAND circuit which performs a NAND operation on output signals of the second and third control circuits; and

a second inverting circuit which inverts an output signal of the third NAND circuit, and

wherein said fifth control circuit comprises;

a third delay circuit which delays the second signal; and

a fourth NAND circuit which performs a NAND operation on an output signal of the third delay circuit and the second signal.