Six-axis surround sound processor with improved matrix and cancellation control

• US 5,625,696 A
• Filed: 04/02/1996
• Issued: 04/29/1997
• Est. Priority Date: 06/08/1990
• Status: Expired due to Term

• Current Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Inventors: Fosgate, James W.
• Primary Examiner(s): Oh, Minsun
• Application Number:
  US08/631,603
• Time in Patent Office: 392 Days
• Field of Search: 381/18, 381/17, 381/19, 381/20, 381/21, 381/22, 381/23
• US Class Current: 381/18
• CPC Class Codes: H04S 3/02 of the matrix type, i.e. in which input signals are combined algebraically, e.g. after having been phase shifted with respect to each other
• CPC Class Codes: H04S 5/005 of the pseudo five- or more-channel type, e.g. virtual surround
• CPC Class Codes: H04S 7/301 Automatic calibration of stereophonic sound system, e.g. with test microphone
• CPC Class Codes: H04S 7/40 Visual indication of stereophonic sound image

Abstract

A surround sound processor for redistribution of stereophonic audio signals into multiple channels for presentation on a plurality of loudspeakers surrounding a listener has an improved direction detector filter circuit, a peak hold circuit in the direction detector for better dynamic separation, improved time constants in the servologic circuit, improved linearity correction in the control voltage generator to match the characteristics of the new voltage controlled amplifiers which are applied to the separation matrix, a separation matrix having cancellation of unwanted signals wihtout gain modification for desired signal components, and improved shelf filters in the rear channel outputs.

Claims

1. A surround sound processor comprising:

audio input terminals for receiving a left and a right audio input signal forming a conventional stereophonic audio signal pair;

an input stage for buffering and balancing said left and right audio input signals and providing output left and right audio signals;

a detector filter circuit receiving the output left and right audio signals and having a band pass characteristic, followed by an inverter circuit and a detector matrix circuit to provide left and right audio signal currents;

a direction detector circuit receiving said left and right audio signal currents and providing therefrom left-right and front-back directional signals, and including peak hold circuitry;

a detector splitter circuit providing left front-right front, left back-right back, and front-back output signals derived from the outputs of said direction detector circuit, and incorporating linearity correction circuitry;

a servologic circuit providing variable time constant smoothing of the output signals from said detector splitter circuit, and producing six output control signals;

voltage controlled amplifier circuits, each controlled by a different one of said six output control signals of said servologic circuit, and each provided with input audio signals that are a combination of said left and right output audio signals from said input stage, each said voltage controlled amplifier circuits being provided with an inverter circuit so as to produce controlled audio signals of both normal and inverted polarity;

a separation matrix circuit for combining the said output left and right audio signals from said input stage with one or more of said output signals from said voltage controlled amplifier circuits in various appropriate proportions so as to provide a plurality of matrix output signals; and

a like plurality of output buffer amplifiers for buffering and level control of said matrix output signals to produce at a like plurality of output terminals a set of loudspeaker feed signals for amplification and application to loudspeakers placed in a listening area so as to surround a listener.

2. The processor of claim 1 wherein said detector filter circuit is a band pass filter circuit having an upper cut-off frequency of approximately 15 kHz and a lower cut-off frequency of approximately 330 Hz, with an attenuation of 20 dB/decade below said lower cut-off frequency.

3. The processor of claim 1 wherein said direction detector circuit incorporates a peak hold circuit having an attack time constant of 0.5 ms and a decay time constant of 5 ms.

4. The processor of claim 1 wherein said detector splitter circuit incorporates linearity correction circuitry comprising a combination of a pair of zener diodes connected in series opposition with a series resistor, in parallel with a fixed resistor, the combination thereof being in the feedback path of an operational amplifier to produce reduced gain at higher input signal amplitudes, and similar combinations being incorporated in the feedback path of one or more additional operational amplifiers forming part of said detector splitter circuit.

5. The processor of claim 1 wherein said six voltage controlled amplifier circuits each comprise an integrated voltage controlled amplifier having logarithmic control characteristics;

an inverting current to voltage converter; and

an inverter.

6. The processor of claim 1 wherein said separation matrix circuit and said detector splitter circuit can be operated either in a six-axis control mode utilizing six of said voltage controlled amplifier circuits, or in a four-axis control mode utilising four of said six voltage controlled amplifier circuits, by disabling said detector splitter circuit.

7. The processor of claim 1 wherein said separation matrix circuit is designed so as to produce cancellation of unwanted signal components in each of said plurality of matrix output signals while not varying the gain of desired components in said matrix output signals.

8. The processor of claim 1 wherein one or more of said plurality of output buffer amplifiers also incorporate shelf filter means having a transfer characteristic approximately -3 dB at 7 kHz and -4.4 dB at 20 kHz.