Automatic cache bypass for instructions exhibiting poor cache hit ratio

• US 5,625,793 A
• Filed: 04/15/1991
• Issued: 04/29/1997
• Est. Priority Date: 04/15/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mirza, Jamshed H.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US07/685,583
• Time in Patent Office: 2,206 Days
• Field of Search: 395/425, 395/400, 364/DIG. 1, 364/243.41, 364/243.43
• US Class Current: 711/138
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A cache bypass mechanism automatically avoids caching of data for instructions whose data references, for whatever reason, exhibit low cache hit ratio. The mechanism keeps a record of an instruction'"'"'s behavior in the immediate past, and this record is used to decide whether its future references should be cached or not. If an instruction is experiencing bad cache hit ratio, it is marked as non-cacheable, and its data references are made to bypass the cache. This avoids the additional penalty of unnecessarily fetching the remaining words in the line, reduces the demand on the memory bandwidth, avoids flushing the cache of useful data and, in parallel processing environments, prevents line thrashing. The cache management scheme is automatic and requires no compiler or user intervention.

Claims

1. In a computer system including a main memory, a processor requesting data from said main memory, and a cache interposed between said processor and said main memory and storing a subset of data in said main memory, an automatic cache bypass mechanism for instructions exhibiting poor cache hit ratio comprising:

cache control means for determining if requested data is in the cache thereby signifying a cache hit, and if so, retrieving the requested data from the cache, but otherwise, retrieving the requested data from said main memory;

table means addressed by an instruction address from said processor for keeping a record of last referenced line addresses and a status of cacheable or noncacheable based on a history of cache hits or misses and for storing a bonus value for cache hits, said bonus value being related to a number of cache hits of said last referenced line addresses and providing a threshold for determining when to switch said last referenced line addresses from a status of cacheable to noncacheable;

means responsive to said cache control means and said table means for storing data retrieved from said main memory into said cache when a current status for the data as recorded in said table means is cacheable and for bypassing said cache when said current status is noncacheable, said cache being bypassed when a number of cache misses for the requested data exceeds the bonus value; and

means for changing the status of data as recorded in said table means as a function of cache hits and said bonus value.

2. The automatic cache bypass mechanism recited in claim 1 further comprising:

means for assigning an initial bonus value to data with a status of cacheable when first storing data in said cache; and

means for modifying said bonus value as a function of cache hits or cache misses for said data.

3. The automatic cache bypass mechanism recited in claim 2 wherein said means for modifying said bonus value reduces the recorded bonus value for each cache miss and said means for changing the status of data changes a status of cacheable, as recorded in said table means, to noncacheable on a cache miss when said bonus value is zero.

4. The automatic cache bypass mechanism recited in claim 3 wherein said means for changing the status of data changes a status of noncacheable, as recorded in said table means, to cacheable on a cache hit, said bonus value remaining zero.

5. The automatic cache bypass mechanism recited in claim 4 wherein said bonus value is a tuning parameter which is determined prior to a running of a program on said computer system.

6. The automatic cache bypass mechanism recited in claim 4 wherein said bonus value is a tuning parameter which is predefined within a program running on said computer system.

7. The automatic cache bypass mechanism recited in claim 4 wherein said cache comprises S lines and said bonus value is around S/4.

8. The automatic cache bypass mechanism recited in claim 4 wherein said bonus value is a tuning parameter which is dynamically varied as a function of cache-miss activity.

9. The automatic cache bypass mechanism recited in claim 1 wherein said means responsive to said cache control means and said table means for storing data in said cache comprises:

means for reading out of said table means said status and bonus value for a line addressed by an instruction address from said processor;

comparator means for determining whether said bonus value is greater than zero; and

gating means responsive to said status, said comparator means and said cache control means for generating a bypass signal to said cache control means.

10. The automatic cache bypass mechanism recited in claim 9 further comprising:

selector means responsive to said bonus value read out of said table means for selecting the greater of either zero or one less than said bonus value;

multiplexer means having as inputs an output of said selector means and a predefined bonus value, said multiplexer means providing as an output said predefined bonus value when said cache control means indicates a cache hit but said output of said selector means when said cache control means indicates a cache miss; and

means for updating the bonus value, as recorded in said table means, with the output of said multiplexer means.

11. The automatic cache bypass mechanism recited in claim 10 wherein said means for changing the status of data, as recorded in said table means, of a line addressed by an instruction address from said processor uses said bypass signal from said gating means to update the status.