Slew rate based power usage simulation and method

• US 5,625,803 A
• Filed: 12/14/1994
• Issued: 04/29/1997
• Est. Priority Date: 12/14/1994
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: McNelly, Andrew J., Seiler, Bruce S., Grossman, Michael R., Misheloff, Michael N., Sarin, Harish K.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NGUYEN, TAN QUANG
• Application Number:
  US08/357,843
• Time in Patent Office: 867 Days
• Field of Search: 395/500, 395/488, 395/489, 395/490, 395/491, 395/578, 395/492, 395/495
• US Class Current: 703/14
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A power usage simulator generates, for all the logic cells in a circuit cell library, a power model that characterizes a cell'"'"'s power consumption behavior as a two-part, piecewise-linear function based on signal slew rates and output load. A logic simulator is modified so that for each signal transition in a specified logic circuit, the logic simulator performs a power usage computation utilizing the power usage model for all cells affected by each signal transition. The power usage value for each signal transition is posted to a power usage output data structure, with each posted power usage value having an associated time value. The posted power usage values are then analyzed by (A) accumulating the posted power usage values to provide a total power usage value, and (B) clocking the accumulation of power usage values with an end user set clock rate so as to produce a power usage profile indicating the time varying rate of power consumption during the simulation time period. The clocked accumulation of power usage enables easy detection of whether the peak rate of power consumption during the simulation time exceeds a specified threshold (e.g., a threshold associated with a particular power bus design). Thus, data generated by the power usage simulation may be used, either directly or indirectly to determine that the simulated logic circuit requires a larger power bus design, or that the logic circuit should be modified so as to reduce its peak power usage rate.

Claims

1. A method for simulating power consumption of an electronic circuit having a plurality of circuit elements, where each said circuit element is an instance of a library cell selected from a predefined set of library cells, said method comprising the steps of:

(a) providing a transistor-level netlist of a cell to be characterized, said cell having an input and an output, said cell comprising one of said set of library cells;

(b) determining a power dissipation profile for said cell by modelling at said transistor-level power dissipated by said cell in response to input waveforms applied to said input of said cell for a plurality of input slew rate and output load combinations, wherein said input slew rate is a signal transition rate associated with said input waveforms and said output load is a capacitive load driven from said output;

said determining step including, when said cell is capable of assuming more than one internal logic state, a plurality of power dissipation profiles corresponding to a plurality of internal logic states for said cell;

(c) characterizing each said power dissipation profile for said cell with a plurality of power coefficients representing power dissipation for said cell as function of said slew rate and said output load;

(d) executing steps (a)-(c) for each of said cells comprising said circuit;

(e) precomputing for each circuit element an input slew rate and an output load;

(f) precomputing for each circuit element a power factor corresponding to each of said power dissipation profiles for the library cell corresponding to said each circuit element, each said power factor being computed as a function of said power coefficients for the corresponding power dissipation profile, said precomputed input slew rate and said precomputed output load;

(g) simulating the logic and timing behavior of said circuit for a specified time period so as to generate data representing simulated signal transitions at computed times in said circuit;

(h) for each said simulated signal transition, storing a power factor for each circuit element, if any, that receives said simulated signal transition, wherein the power factor stored is the one of said precomputed power factors for said circuit element corresponding to said circuit element'"'"'s simulated state, if any, just prior to said simulated signal transition;

wherein said characterization of said cell constituted as a single-stage device further comprises the steps of;

(i) measuring a first power (P1) corresponding to a first input ramp (IR1) in a fast ramp region and a first output load (LOAD1) in a low load region, wherein said fast ramp region defines a part of said power dissipation profile where, for a constant output load, power dissipated by said cell is relatively independent of input ramp;

(j) measuring a second power (P2) corresponding to a second input ramp (IR2) in said fast ramp region and said first output load (LOAD1);

(k) measuring a third power (P3) corresponding to said first input ramp (IR1) and a second output load (LOAD2) in a high load region;

(l) measuring a fourth power (P4) corresponding to a fourth input ramp (IR4) from a slow ramp region and an output load in said low load region, wherein said slow ramp region defines a part of said power dissipation profile where, for a constant output load, power dissipated by said cell increases as said input ramp increases;

(m) determining a critical input ramp (CIR) for said power dissipation profile, where said CIR is a curve separating said fast ramp and said slow ramp regions of said power dissipation probe;

(n) computing a first coefficient (D) as follows;

D=(P2-P1)/(IR2-IR1);

(o) computing a second coefficient (B) as follows;

B=(P3-P1)/(LOAD3-LOAD1);

(p) computing a third coefficient (A) as follows;

A=P3-B*LOAD3-D*IR1; and

(q) computing a fourth coefficient (E) as follows;

E=((P4-P1)-D*CIR)/(IR4-CIR)

such that, given an input ramp, an output load; and

a state of said cell, a measure of dynamic and static power dissipated by said cell as a result of a pin-pair transition on said input and said output of said cell can be determined according to the following formula;

space="preserve" listing-type="equation">P=A+B*LOAD+D*min(IR, CIR)+E*max(0,IR-CIR),

which approximates said power dissipation profile in a piecewise linear fashion, said approximation consisting of a first line segment having a first slope defining said fast ramp region and a second line segment having a second slope defining said slow ramp region, said first line segment and said second line segment intersecting at a single point located on said CIR.

2. The method of claim 1 wherein said critical input ramp (CIR) for said power dissipation profile is identical to a critical input ramp (TCIR) for the timing behavior of said cell determined during a delay simulation of said cell, said TCIR being defined as 1/2(DT0+DT1), where DT0 is a linear function representing time measured during said delay simulation between a signal transition beginning at said input of said cell and a signal transition beginning at said output of said cell, and DT1 is a different linear function representing time measured during said delay simulation between a signal transition beginning at said input of said cell and a signal transition ending at said output of said cell, said DT0 and DT1 intersecting at said single point.

3. The method of claim 1, further including:

(a) specifying a sequence of time periods;

(b) accumulating said power factors stored for each time period in said sequence of time periods so as to generate a total power dissipation factor for each said time period; and

(c) generating a representation of power dissipation by said electronic circuit for each said time period.

4. The method from claim 1 wherein said power dissipation profiles reflect dynamic and static power dissipation of said cell to be characterized.

5. The method of claim 1 wherein said power dissipated in said electronic circuit is stored in such a manner that static and dynamic power dissipated by instances, static and dynamic power dissipated in the entire circuit, and power dissipated in various blocks, subblocks or other designated regions of said circuit can be reported for each computed time period.

7. The method of claim 1 or 6 wherein, when said cell is a multi-stage device, said power dissipation profile of said cell is approximated as a linear function.

6. A method for simulating power consumption of an electronic circuit having a plurality of circuit elements, where each said circuit element is an instance of a library cell selected from a predefined set of library cells, said method comprising the steps of:

(a) providing a transistor-level netlist of a cell to be characterized, said cell having an input and an output, said cell comprising one of said set of library cells;

(b) determining a power dissipation profile for said cell by modelling at said transistor-level power dissipated by said cell in response to input waveforms applied to said input of said cell for a plurality of input slew rate and output load combinations, wherein said input slew rate is a signal transition rate associated with said input waveforms and said output load is a capacitive load driven from said output;

said determining step including, when said cell is capable of assuming more than one internal logic state, a plurality of power dissipation profiles corresponding to a plurality of internal logic states for said cell;

(c) characterizing each said power dissipation profile for said cell with a plurality of power coefficients representing power dissipation for said cell as function of said input slew rate and said output load, said power coefficients defining a piecewise linear approximation of said power dissipation profile, said approximation consisting of at least two line segments having slopes relating dissipated power to output load and input slew rate, adjacent pairs of said line segments meeting at a single point located on a critical input ramp (CIR) for said power dissipation profile that is identical to a critical input ramp (TCIR) for the timing behavior of said cell determined during a delay simulation of said cell, said TCIR being defined as 1/2(DT0+DT1), where DT0 is a linear function representing time measured between a signal transition beginning at said input of said cell and a signal transition beginning at said output of said cell, and DT1 is a different linear function representing time measured between a signal transition beginning at said input of said cell and a signal transition ending at said output of said cell, said DT0 and DT1 intersecting at said single point;

(d) executing steps (a)-(c) for each of said cells comprising said circuit;

(e) precomputing for each circuit element an input slew rate and an output load;

(f) precomputing for each circuit element a power factor corresponding to each of said power dissipation profiles for the library cell corresponding to said each circuit element, each said power factor being computed as a function of said power coefficients for the corresponding power dissipation profile, said precomputed input slew rate and said precomputed output load;

(g) simulating the logic and timing behavior of said circuit so as to generate data representing simulated signal transitions in said circuit;

(h) for each said simulated signal transition, storing a power factor for each circuit element, if any, that receives said simulated signal transition, wherein the power factor stored is the one of said precomputed power factors for said circuit element corresponding to said circuit element'"'"'s simulated state, if any, just prior to said simulated signal transition.

8. A power simulator to simulate power consumption behavior of an electronic circuit having a plurality of instances copied from a library of cells, said simulator comprising:

(a) a physical design tool to provide a transistor- level description of a cell to be characterized, said cell having an input and an output;

(b) a circuit simulator to determine a power dissipation profile for said cell based on said cell'"'"'s transistor-level description by modelling at said transistor-level power dissipated by said cell in response to input waveforms applied to said input of said cell for a plurality of input ramp and output load combinations, wherein said input ramp is a slew rate associated with said input waveforms and said output load is a capacitive load driven from said output;

(c) a characterization routine to generate a plurality of power coefficients that model said cell'"'"'s power dissipation profile as a function of input-output transitions and states of said cell, wherein said input-output transitions and said states are a byproduct of said input waveforms, said power coefficients defining a piecewise linear approximation of said power dissipation profile, said approximation consisting of at least two line segments having slopes relating dissipated power to output load and input slew rate, adjacent pairs of said line elements meeting at a single point located on a critical input ramp (CIR) for said power dissipation profile that is identical to a critical input ramp (TCIR) for the timing behavior of said cell determined during a delay simulation of said cell, said TCIR being defined as 1/2(DT0+DT1), where DT0 is a linear function representing time measured between a signal transition beginning at said input of said cell and a signal transition beginning at said output of said cell, and DT1 is a different linear function representing time measured between a signal transition beginning at said input of said cell and a signal transition ending at said output of said cell, said DT0 and DT1 intersecting at said single point;

(d) a netlister to determine for each instance an instance input ramp and an instance output load based on a logic device level netlist of said electronic circuit;

(e) a precomputer to compute for each instance power factors relating power dissipation in said instance to said input-output transitions and said states of said instance, wherein said power factors are based on said power coefficients of a cell from which said instance was copied and said instance input ramp and said instance output load;

(f) an event driven logic simulator to simulate the logic and timing behavior of said circuit in response to event stimulus vectors and generate data representing simulated signal transitions at computed times in said circuit;

(g) a power module to store for each simulated signal transition a power factor for each instance, if any, that receives said simulated signal transition, wherein the power factor stored is one of said precomputed power factors for said circuit element corresponding to said circuit element'"'"'s simulated state, if any, just prior to said simulated signal transition.

9. The method of claim 8 wherein said cell power coefficients are generated by a selectable power precomputer.

10. A method for simulating power consumption of an electronic circuit having a plurality of circuit elements, where each said circuit element is an instance of a library cell selected from a predefined set of library cells, said method comprising the steps of:

(a) providing a transistor-level netlist of a cell to be characterized, said cell having an input and an output, said cell comprising one of said set of library cells;

(b) determining a power dissipation profile for said cell by modelling at said transistor-level power dissipated by said cell in response to input waveforms applied to said input of said cell for a plurality of input slew rate and output load combinations, wherein said input slew rate is a signal transition rate associated with said input waveforms and said output load is a capacitive load driven from said output;

said determining step including, when said cell is capable of assuming more than one internal logic state, a plurality of power dissipation profiles corresponding to a plurality of internal logic states for said cell;

(c) characterizing each said power dissipation profile for said cell with a plurality of power coefficients representing power dissipation for said cell as function of said slew rate and said output load;

(d) executing steps (a)-(c) for each of said cells comprising said circuit;

(e) precomputing for each circuit element an input slew rate and an output load;

(f) precomputing for each circuit element a power factor corresponding to each of said power dissipation profiles for the library cell corresponding to said each circuit element, each said power factor being computed as a function of said power coefficients for the corresponding power dissipation profile, said precomputed input slew rate and said precomputed output load;

(g) simulating the logic and timing behavior of said circuit for a specified time period so as to generate data representing simulated signal transitions at computed times in said circuit;

(h) for each said simulated signal transition, storing a power factor for each circuit element, if any, that receives said simulated signal transition, wherein the power factor stored is the one of said precomputed power factors for said circuit element corresponding to said circuit element'"'"'s simulated state, if any, just prior to said simulated signal transition;

wherein said characterization of said cell constituted as a multi-stage device comprises the steps of;

(i) measuring a fifth power (P5) corresponding to a fifth input ramp (IR5) in a fast ramp region and a fifth output load (LOAD5) in a high load region, wherein said fast ramp region defines a part of said power dissipation profile where, for a constant output load, power dissipated by said cell is relatively independent of input ramp;

(j) measuring a sixth power (P6) corresponding to a sixth input ramp (IR2) different from said fifth input ramp (IR5) and a sixth output load (LOAD6) in a high load region;

(k) measuring a seventh power (P7) corresponding to said sixth input ramp (IR6) and said fifth output (LOAD5);

(l) creating a system of three equations in three variables by substituting triplets (P5, IR5, LOAD5), (P6, IR2, LOAD6), and (P7, IR6, LOAD5) into an equation defining power dissipation of a multi-stage cell in the high load region, said high load equation given by the expression P=Ahigh+Bhigh*IR+Dhigh*LOAD, said triplets being substituted for the variables P, IR and LOAD; and

(m) solving said system of three equations in three variables for said high load power coefficients, Ahigh, Bhigh and Dhigh;

(n) measuring an eighth power (P8) corresponding to said sixth input ramp (IR6) in a fast ramp region and an eighth output load (LOAD8) in a low load region;

(o) measuring a ninth power (P9) corresponding to said fifth input ramp (IR5) and a ninth output (LOAD9) in a low load region;

(p) measuring a tenth power (P10) corresponding to said sixth input ramp (IR6) and said ninth output load (LOAD9);

(q) creating a system of three equations in three variables by substituting triplets (P8, IR6, LOAD8), (P9, IR5, LOAD9), and (P10, IR6, LOAD9) into an equation defining power dissipation of a multi-stage cell in the low load region, said low load equation being given by the expression P=Alow+Blow*IR+Dlow*LOAD, said triplets being substituted for the variables P, IR and LOAD; and

(r) solving said system of three equations in three variables for said low load power coefficients, Alow, Blow and Dlow;

such that, given an input ramp, an output load, and a state of said cell, a measure of dynamic and static power dissipated by said cell as a result of a pin-pair transition on said input and said output of said cell can be determined according to the formula P=Ahigh+Bhigh*LOAD+Dhigh*IR, if said output load is in said high load region; and

according to the formula P=Alow+Blow*LOAD+Dlow*IR, if said output load is in said low load region, said equations each approximating said power dissipation profile as a single line.

11. The method of claim 10, further including:

(a) specifying a sequence of time periods;

(b) accumulating said power factors stored for each time period in said sequence of time periods so as to generate a total power dissipation factor for each said time period; and

(c) generating a representation of power dissipation by said electronic circuit for each said time period.

12. The method of claim 10 wherein said power dissipation profiles reflect dynamic and static power dissipation of said cell to be characterized.

13. The method of claim 10 wherein said power dissipated in said electronic circuit is stored in such a manner that static and dynamic power dissipated by instances, static and dynamic power dissipated in the entire circuit, and power dissipated in various blocks, subblocks or other designated regions of said circuit can be reported for each computed time period.