SIMD/MIMD processing memory element (PME)

• US 5,625,836 A
• Filed: 06/02/1995
• Issued: 04/29/1997
• Est. Priority Date: 11/13/1990
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Richardson, Robert R., Retter, Eric E., Dapp, Michael C., Barker, Thomas N., Nier, Richard E., Dieffenderfer, James W., Lesmeister, Donald M., Smoral, Vincent J., Collins, Clive A.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US08/459,374
• Time in Patent Office: 697 Days
• Field of Search: 395/800, 395/275, 395/325, 395/575, 395/375, 395/775, 370/80
• US Class Current: 709/214
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17368 non hierarchical topologies
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Abstract

A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

Claims

1. A multi-processor memory system, comprising:

a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, each of said processing memory elements having a processor coupled with a dedicated local memory;

means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.

2. A multi-processor memory system according to claim 1 wherein there are plural copies of a processor embedded in a memory on the substrate which functions as a system node, and a means for changing under programmable control SIMD/MIMD functions as a multi-processor memory system at each node.

3. A multi-processor memory system according to claim 1 wherein each multi-processor memory element (PME) of the system is on a chip having

multi-byte internal data flow and control;

means for data and control communications;

sufficient local storage for enabling MIMD local mode operation and data storage;

circuit switched mode and store and forward mode;

an on chip PME to PME communication network; and

means for switching dynamically between SIMD and MIMD modes.

4. A multi-processor memory system according to claim 1 wherein each processor memory element comprises a 16-bit processing memory element with full 16-bit internal control and data flow for PME to PME communication within a network defined binary hypercube for said common substrate as a node, each node processor memory element having 16-bit internal data flow and control enabling high performance data manipulation and I/O operations.

5. A multi-processor memory system according to claim 1 having a 16 bit RISC ISA which permits decoded instructions to come from either internal memory via normal decode or from a broadcast bus connected in common to the multi-processor memory elements, thus permitting the mixture of SIMD and MIMD modes in the same machine.

6. A multi-processor memory system according to claim 1 further comprising within a processor memory element:

means for dynamic switching between SIMD and MIMD modes of operation enabling dual SIMD/MIMD operation and group partitioned SIMD/MIMD operation.

7. A multi-processor memory system according to claim 1 further comprising within a processor memory element:

means for dynamic switching between SIMD and MIMD modes of operation enabling dual SIMD/MIMD memory utilization for conversion routines and group partitioned SIMD/MIMD table value and fast fourier routines.

8. A multi-processor memory system according to claim 1 further comprising within a processor memory element:

means for dynamic switching between SIMD and MIMD modes of operation for store and forward functions and circuit switched functions which enable message and data transferring.

9. A multi-processor memory system according to claim 1 further comprising within a processor memory element:

means for switching between SIMD and MIMD modes of operation for fast fourier transform and sorting.

10. A multi-processor memory system according to claim 1 further comprising within a processor memory element:

means for operating in SIMD or MIMD mode.

11. A multi-processor memory system according to claim 1 further comprising within a processing memory element:

means for operating in SIMD or MIMD mode, and wherein a set of processor memory elements can be divided into subgroups that operate in different modes.

12. A multi-processor memory system according to claim 1 further comprising within a processing memory element:

means for operating in SIMD or MIMD mode, and wherein a set of processor memory elements can be divided into subgroups that operate in different modes, with MIMD input groups, SIMD processing groups and MIMD output functions.

13. A multi-processor memory system according to claim 1 further comprising within a processing memory element:

means for operating a processor memory element in MIMD mode and to switch between interrupt levels for managing input/output and routing functions associated with input/output.

14. A multi-processor memory system according to claim 1 wherein the processor of said processor memory element is a RISC processor with an instruction architecture which enables decoded instruction to originate from either internal memory via a normal instruction decode, or from a communication path functioning as a broadcast bus, and said instruction architecture enables a processor memory element to function in either SIMD mode or MIMD mode.

15. A multi-processor memory system according to claim 1 wherein the processor of said processor memory element is a RISC processor with an instruction architecture which enables a processor memory element to function in either SIMD mode or MIMD mode.

16. A multi-processor memory system according to claim 1 wherein a node forms part of a cluster, each node having a set of multiple processor memory elements, and wherein a complete set of processor memory element may be divided into 1 to many distinct subsets under control of an array director to interleave between subsets to operate distinct subsets of the array in one mode while other sets operate in tightly synchronized SIMD mode under array director control.

17. A multi-processor memory system according to claim 1 wherein a node processor memory element instruction decode logic permits the processor memory element to operate in either SIMD mode or MIMD mode, transitions between each mode occurring dynamically.

18. A multi-processor memory system according to claim 1 wherein a node processing memory element in SIMD mode receives decoded instruction information and executes that data in the next clock cycle.

19. A multi-processor memory system according to claim 1 wherein a node processing memory element in MIMD mode maintains a program counter PC address and uses that as the address within its own memory to fetch an instruction.

20. A multi-processor memory system according to claim 1 wherein a node processing memory element in SIMD mode enters MIMD mode when given information that represents a decode branch.

21. A multi-processor memory system according to claim 1 wherein a node processing memory element in MIMD mode enters SIMD mode upon executing a specific instruction for the transition.