Method and apparatus for measuring the period of response of an implantable medical device based upon the difference in phase between a trigger signal and an internal clock signal

• US 5,626,625 A
• Filed: 01/25/1996
• Issued: 05/06/1997
• Est. Priority Date: 11/01/1994
• Status: Expired due to Fees

• Current Assignee: Intermedics Incorporated
• Original Assignee: Intermedics Incorporated
• Inventors: Fernald, Kenneth W.
• Primary Examiner(s): Kamm, William E.
• Assistant Examiner(s): LAYNO, CARL HERNANDZ
• Application Number:
  US08/591,317
• Time in Patent Office: 467 Days
• Field of Search: 607/32, 607/60, 128/903
• US Class Current: 607/32
• CPC Class Codes: A61N 1/3727 characterised by the modulation technique
• CPC Class Codes: G01R 25/005 Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: Y10S 128/903 Radio telemetry

Abstract

A method and apparatus is disclosed for use in an implantable device that communicates with an external device through pulse position modulation. A timing generator is provided as part of the implantable device that determines the phase uncertainty between an external signal and an internal cock signal. The phase uncertainty then is added to the preset delay period to more precisely control the position of the response. The phase uncertainty is measured by a dual slope circuit that varies a state variable (which can be a digital timer, a capacitor voltage, or the like) at a fixed rate with either a positive or negative slope. When the external signal is detected, the stat variable is reset and then decreased at a fixed rate until the next positive edge of the clock signal. The state variable then is increased at the same rate until the subsequent positive clock edge. The resulting variable value is proportional to the phase uncertainty. When the delay timer reaches zero, the state variable is again decreased at the same fixed rate until the initial value is reached, at which the output response is generated.

Claims

1. A method for measuring phase difference between a trigger signal and an internal clock signal in an implantable device, said phase difference indicating the period of response of the implantable device after the trigger signal is received by the implantable device, said method comprising the steps of:

setting a state variable equal to an initial value;

changing the value of the state variable from the initial value at a first fixed rate after receiving the trigger signal;

changing the value of the state variable at a second fixed rate opposite in polarity to said first fixed rate when a first clock edge of said clock signal occurs subsequent to receiving the trigger signal;

beginning to count a preset period when said first clock edge occurs;

maintaining the value of the state variable when a second clock edge of said clock signal occurs;

completing the count of said preset period;

changing the value of the state variable at said first fixed rate after said count of said preset period is completed; and

producing an output signal when said state variable returns to said initial value.

2. A method as in claim 1, wherein the first fixed rate is M and the second fixed rate is zero.

3. A method as in claim 2, wherein the value of the state variable is changed at a rate of -M after the count of the preset period is complete.

4. A method as in claim 1, wherein said first fixed rate has a slope -M, and said second fixed rate has a slope M, so that the first fixed rate has a slope that is the opposite of said second fixed rate.

5. A method as in claim 4, wherein said initial value is zero.

6. A method as in claim 5, wherein said first clock edge is a rising clock edge.

7. A method as in claim 6, wherein said second clock edge is a rising clock edge.

8. A method as in claim 7, wherein said count of said preset period only proceeds at rising clock edges of said clock signal.

9. A method as in claim 5 wherein said first clock edge is a falling clock edge.

10. A method as in claim 9, wherein said second clock edge is a rising clock edge.

11. A method for determining a period of response for an implantable medical device based upon a difference in phase between an external trigger signal and an internal clock signal in the implantable medical device, said method comprising the steps of:

storing a state variable with an initial value;

changing the value of the state variable at a first constant rate after detection of the trigger signal and until occurrence of a first clock edge of the internal clock signal;

loading a preset period into a counter upon detection of the external trigger signal;

changing the value of the state variable at a second fixed rate opposite in polarity to said first fixed rate after occurrence of the first clock edge;

initializing the counter to count the preset period after occurrence of said first clock edge;

maintaining the value of the state variable after occurrence of a second clock edge of said internal clock signal;

changing the value of the state variable at said first fixed rate after said count of said preset period is completed by said counter; and

producing an output signal for the implantable device in response to the trigger signal when said state variable returns to said initial value.

12. A method as in claim 11, wherein said initial value is zero.

13. A method as in claim 11 wherein the end of said preset period defines a response synchronized with said trigger signal.

14. A method as in claim 11, wherein said first and second clock edges are different edge types.

15. A method as in claim 11, wherein said first and second clock edges are the same edge type.

16. A method as in claim 15, wherein the first and second clock edges are both rising clock edges.

17. A method as in claim 15, wherein the first and second clock edges are both falling clock edges.