Method for fabricating MIS semiconductor device

• US 5,627,084 A
• Filed: 01/18/1994
• Issued: 05/06/1997
• Est. Priority Date: 01/18/1993
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US08/181,907
• Time in Patent Office: 1,204 Days
• Field of Search: 437/21, 437/41, 437/101, 257/57, 257/66
• US Class Current: 438/166
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.

Claims

1. A method for fabricating a MIS semiconductor device comprising:

a first step of forming a wiring comprising an anodizable material on an active region provided in a semiconductor with an insulating film between said wiring and said active region;

a second step of anodizing the surface of said wiring, to form an anodic oxide;

a third step of injecting an impurity into the semiconductor in a self-aligning manner using said wiring or a region defined by said wiring substantially as a mask after the anodization;

a fourth step of removing the anodic oxide after the injecting step;

a fifth step of improving a crystallinity of an impurity region in said semiconductor into which the impurity has been injected by rendering a boundary between said impurity region and said active region or a portion adjacent thereto substantially transparent to light to be radiated and by radiating said light from thereabove.

2. The method of claim 1 further comprising a step of anodizing said wiring again after the fifth step.

3. The method of claim 1 wherein a part or all of the second step is carried out in a reduced pressure plasma atmosphere.

4. The method of claim 1 wherein the said light is a laser light or a light having a light intensity equivalent to that of the laser light.

5. A method for fabricating a MIS semiconductor device comprising:

forming a gate electrode comprising an anodizable material on a gate insulating film provided on an active region provided in a semiconductor;

anodizing said gate electrode to form an anodic oxide on a surface of said gate electrode;

injecting an impurity into said semiconductor in a self-aligning manner using said anodic oxide as a mask;

removing said anodic oxide after said injecting step; and

irradiating a light to an impurity region in said semiconductor into which said impurity is injected by said injecting step, and to a boundary between said impurity region and said active region with said gate electrode as a mask after said removing step to improve a crystallinity of said semiconductor of said boundary and said impurity region.

6. The method of claim 5 wherein said light is a laser light or a light having a light intensity equivalent to that of the laser light.

7. The method of claim 5 wherein said removing step is carried out by etching in a plasma atmosphere comprising CF₄ and O₂.

8. The method of claim 7 wherein ratio CF₄ /O₂ is 3 to 10 in terms of flow rate.

9. The method of claim 5 wherein said gate electrode comprises a material having a melting point of 3000°

C. or higher.

10. The method of claim 5 further comprising the step of anodizing said gate electrode after said irradiating step.

11. A method for fabricating a MIS semiconductor device comprising:

forming a gate electrode comprising an anodizable material on a gate insulating film provided on an active region provided in a semiconductor;

anodizing said gate electrode to form a first anodic oxide on a surface of said gate electrode;

injecting an impurity into said semiconductor in a self-aligning manner using said first anodic oxide as a mask;

removing said first anodic oxide after said injecting step;

irradiating a light to an impurity region in said semiconductor into which said impurity is injected by said injecting step, and to a boundary between said impurity region and said active region with said gate electrode as a mask after said removing step to improve a crystallinity of said semiconductor of said boundary and said impurity region; and

anodizing said gate electrode to form a second anodic oxide on the surface of said gate electrode after said irradiating step.

12. A method for fabricating a MIS semiconductor device comprising:

forming a gate electrode comprising an oxidizable material on a gate insulating film provided on an active region provided in a semiconductor;

oxidizing said gate electrode to form an oxide on a surface of said gate electrode;

injecting an impurity into said semiconductor in a self-aligning manner using said oxide as a mask;

removing said oxide after said injecting step; and

irradiating a light to an impurity region in said semiconductor into which said impurity is injected by said injecting step, and to a boundary between said impurity region and said active region with said gate electrode as a mask after said removing step to improve a crystallinity of said semiconductor of said boundary and said impurity region.

13. A method for producing a semiconductor device comprising the steps of:

forming a first electrode wiring including an anodizable material on an insulating film provided on a semiconductor film having an active region and an impurity region;

anodizing the first electrode wiring to form a first anodic oxide on a surface of the first electrode wiring;

introducing an impurity into the semiconductor film using the first anodic oxide as a mask;

removing the first anodic oxide after the introducing step;

irradiating a light to the impurity region into which the impurity has been introduced and to a boundary between the impurity region and the active region using the first electrode wiring as a mask after the removing step, to improve a crystallinity of the impurity region and the boundary;

forming a covering film to cover the first electrode wiring;

anodizing at least one second electrode wiring other than the first electrode wiring to form a second anodic oxide on a surface of the second electrode wiring; and

forming a third electrode wiring on the second anodic oxide.

14. A method for producing a semiconductor device comprising the steps of:

forming a gate electrode including an anodizable material on an insulating film provided on a semiconductor film having an active region and an impurity region;

anodizing the gate electrode to form an anodic oxide on a surface of the gate electrode;

introducing an impurity into the semiconductor film using the anodic oxide as a mask;

etching the anodic oxide to decrease a thickness of the anodic oxide after the introducing step; and

irradiating a light to the impurity region into which the impurity is introduced and to a boundary between the impurity region and the active region using the gate electrode and the etched anodic oxide as masks after the removing step, to improve a crystallinity of the impurity region and the boundary.