Method for making CMOS device having reduced parasitic capacitance

• US 5,627,097 A
• Filed: 07/03/1995
• Issued: 05/06/1997
• Est. Priority Date: 07/03/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Venkatesan, Suresh, Lutze, Jeffrey, Poon, Stephen
• Primary Examiner(s): Tsai, Jey
• Assistant Examiner(s): Pham, Long
• Application Number:
  US08/498,709
• Time in Patent Office: 673 Days
• Field of Search: 437/40, 437/41, 437/56, 437/57, 437/58, 437/89, 437/63, 437/67, 437/29
• US Class Current: 438/217
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence

Abstract

A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20'"'"') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).

Claims

1. A process for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate having an undoped silicon layer overlying a buried layer;

forming a trench isolation structure in the undoped silicon layer to define an active region therein;

forming a masking layer on the undoped silicon layer, the masking layer having an opening therein exposing a channel portion of the active region;

doping the channel portion with a first dopant, using the masking layer as a doping mask, wherein the first dopant extends from an upper surface of the undoped silicon layer to the buried layer;

depositing a layer of polycrystalline silicon to overlie the masking layer and the channel portion;

planarizing the polycrystalline silicon to form a gate electrode overlying the channel portion;

removing the masking layer; and

forming source and drain regions in the undoped silicon layer on either side of the gate electrode, wherein the source and drain regions are vertically separated from the buried layer by a portion of the undoped silicon layer.

2. The process of claim 1, wherein the step of forming source and drain regions comprises ion implantation of dopant species, wherein the undoped silicon layer is deposited to a first thickness, and wherein the source region has a maximum junction depth which is less than the first thickness of the undoped silicon layer the drain region has a maximum junction depth which is less than the first thickness of the undoped silicon layer.

3. The process of claim 1 further comprising the step of etching a recess in the channel portion of the undoped silicon layer using the masking layer as an etching mask.

4. The process of claim 3 further comprising the step of forming insulating sidewall spacers adjacent to the gate electrode.

5. The process of claim 1, wherein the steps of providing a buried layer and forming a trench isolation structure comprise:

implanting the semiconductor substrate with a second dopant to form an annular doped region in the semiconductor substrate; and

etching a trench in the undoped epitaxial layer such that the trench is subtended by the annular doped region.

6. A process for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate having an undoped epitaxial layer overlying a buried layer of a first conductivity type;

forming a masking layer on the undoped epitaxial layer, the masking layer having an opening therein exposing a channel portion of the undoped epitaxial layer;

doping the channel portion with a dopant of the first conductivity type, using the masking layer as a doping mask;

forming a gate electrode in the opening; and

forming source and drain regions in the undoped epitaxial layer on either side of the gate electrode, wherein the source and drain regions are vertically separated from the buried layer by a portion of the undoped epitaxial layer.

7. The process of claim 6, wherein the step of doping the channel portion comprises forming a continuous doped region extending from an upper surface of the undoped epitaxial layer to the buried layer.

8. The process of claim 6, further comprising the step of forming a dielectric isolation region in the undoped epitaxial layer, and wherein the step of providing a buried layer comprises forming a continuous doped region subtending the dielectric isolation region.

9. The process of claim 6 further comprising the step of etching a recess in the channel portion of the undoped epitaxial layer using the masking layer as an etching mask.

10. A process for fabricating a semiconductor device comprising the steps of:

providing a semiconductor substrate having a surface;

forming a first buried layer of a first conductivity type at the surface;

forming a second buried layer of a second conductivity type at the surface adjacent to the first buried layer;

forming an undoped epitaxial layer overlying the first and second buried layers;

forming an isolation region in the undoped epitaxial layer to define a first active region overlying the first buried layer and a second active region overlying the second buried layer;

forming a masking pattern overlying the undoped epitaxial layer and the isolation region, the masking pattern having a first opening therein exposing a channel portion of the first active region and a second opening therein exposing a channel portion of the second active region;

doping the channel portion of the first active region with a dopant of the first conductivity type;

doping the channel portion of the second active region with a dopant of the second conductivity type;

forming a first gate electrode in the first opening and a second gate electrode in the second opening;

forming source and drain regions of the second conductivity type on either side of the first gate electrode; and

forming source and drain regions of the first conductivity type on either side of the second gate electrode,

wherein the source and drain regions of the second conductivity type are spaced apart from the first buried layer by a first portion of the undoped epitaxial layer, and

wherein the source and drain regions of the first conductivity type are spaced apart frozen the second buried layer by a second portion of the undoped epitaxial layer.

11. The process of claim 10, wherein a portion of the isolation region surrounds the second active region, and wherein the step of forming a second buried layer comprises forming a continuous doped region subtending the portion of the isolation region.

12. The process of claim 10, wherein the step of doping the channel portion of the first active region comprises forming a doped region extending from the surface of the undoped epitaxial layer to the first buried layer.

13. The process of claim 10, wherein the step of doping the channel portion of the second active region comprises forming a doped region extending from the surface of the undoped epitaxial layer to the second buried layer.