Adhesion between dielectric layers in an integrated circuit

• US 5,627,403 A
• Filed: 06/06/1995
• Issued: 05/06/1997
• Est. Priority Date: 05/31/1993
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Zanotti, Luca, Bacchetta, Maurizio, Bacci, Laura
• Primary Examiner(s): Brown, Peter Toby
• Application Number:
  US08/473,552
• Time in Patent Office: 700 Days
• Field of Search: 257/758-760, 257/639-641, 257/644
• US Class Current: 257/639
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02131 the material being halogen doped silicon oxides, e.g. FSG
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/31608 Deposition of SiO2 H01L21/31625, H01L21/31629 and H01L21/31633 take precedence
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31625 Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/902 Capping layer
• CPC Class Codes: Y10S 438/958 : Passivation layer

Abstract

A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material, specifically silicon oxynitride or silicon nitride, on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material (silicon oxynitride or silicon nitride particularly) overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2), silicon dioxide in the preferred embodiment, is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

Claims

1. An integrated circuit, comprising:

a substrate of a semiconductor material;

a first patterned conductor layer formed over said substrate;

a dielectric; and

a second upper patterned conductor layer;

wherein said dielectric comprises;

a first layer of a first silicon nitride compound;

a thin silicon dioxide layer in contact with said first layer of said first silicon nitride compound at least in a region; and

a second layer of a second silicon nitride compound overlaying said first layer of said first silicon nitride compound at least in said region and in contact with said thin silicon dioxide layer at least in said region;

the thickness of said thin silicon dioxide being less than both the thicknesses of said first and second layers of said first and second silicon nitride compounds

wherein the thickness of said thin silicon dioxide layer is in the range between 5 and 50 nm.

2. An integrated circuit according to claim 1, wherein said silicon dioxide is undoped and is formed by means of a CVD technique using TEOS.

3. An integrated circuit according to claim 1, wherein said silicon dioxide is doped with phosphorus.

4. An integrated circuit according to claim 1, wherein said silicon dioxide is doped with boron.

5. An integrated circuit according to claim 1, wherein said silicon dioxide is formed by thermal process using TEOS-O₃.

6. An integrated circuit according to claim 1, wherein said first and second silicon nitride compounds are constituted by either a silicon oxynitride or stoichiometric silicon nitride.

7. An integrated circuit, comprising:

a substrate of a semiconductor material;

a patterned conductor layer formed over said substrate; and

a protective overcoat;

wherein said protective overcoat comprises;

a first layer of a first silicon nitride compound;

a thin silicon dioxide layer in contact with said first layer of said first silicon nitride compound at least in a region; and

a second layer of a second silicon nitride compound over-laying said first layer of said first silicon nitride compound at least in said region and in contact with said thin silicon dioxide layer at least in said region;

the thickness of said thin silicon dioxide being less than both the thicknesses of said first and second layers of said first and second silicon nitride compounds

wherein the thickness of said thin silicon dioxide layer is in the range between 5 and 50 nm.

8. An integrated circuit according to claim 7, wherein said silicon dioxide is undoped and is formed by means of a CVD technique using TEOS.

9. An integrated circuit according to claim 7, wherein said silicon dioxide is doped with phosphorus.

10. An integrated circuit according to claim 7, wherein said silicon dioxide is doped with boron.

11. An integrated circuit according to claim 7, wherein said silicon dioxide is formed by thermal process using TEOS-O₃.

12. An integrated circuit according to claim 7, wherein said first and second silicon nitride compounds are constituted by either a silicon oxynitride or stoichiometric silicon nitride.