Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same

• US 5,627,779 A
• Filed: 07/21/1995
• Issued: 05/06/1997
• Est. Priority Date: 07/22/1994
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Mori, Toshiki, Asai, Akira, Odake, Yoshinori, Okuda, Yasushi, Nakao, Ichirou
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/505,638
• Time in Patent Office: 655 Days
• Field of Search: 365/185.01, 365/185.02, 365/185.2, 365/185.26, 365/185.18, 365/185.12, 257/315, 257/316, 257/322
• US Class Current: 365/185.01
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

Claims

1. A non-volatile semiconductor memory comprising:

an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a channel region, a source, and a drain;

a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array;

a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array;

a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array;

a row decoder circuit for selecting among said plurality of wordlines;

a column decoder circuit for selecting among said plurality of bitlines;

a source decoder circuit for selecting among said plurality of sourcelines;

a plurality of anisotropic resistance sections;

wherein;

each said anisotropic resistance section is arranged in a path from a said bitline to a said sourceline through a said transistor, said anisotropic resistance section is arranged between said channel region of the transistor and said bitline;

each said anisotropic resistance section has voltage-current properties which are different for different levels of voltages applied across said anisotropic resistance section;

each said anisotropic resistance section has a forward direction in which a current flows therethrough with lesser resistance and a reverse direction in which a current flows therethrough with greater resistance, said anisotropic resistance section has properties such that resistance to a current flowing from said memory cell to said bitline is larger than resistance to a current flowing from said bitline to said memory cell.

2. A non-volatile semiconductor memory according to claim 1 wherein:

said anisotropic resistance section is a diode capable of permitting a current to pass therethrough in one direction only.

3. A non-volatile semiconductor memory according to claim 2 wherein:

said diode is a Schottky diode formed by depositing a conductive layer directly on a semiconductor substrate surface region acting as a source or drain of said transistor.

4. A non-volatile semiconductor memory according to claim 2 wherein:

said diode is a PN diode formed between an internal region of a semiconductor substrate acting as a source or drain of said transistor and a contact region of said semiconductor substrate.

5. A non-volatile semiconductor memory according to claim 1 wherein:

said anisotropic resistance section is an offset region formed by implanting, between a drain of said transistor and an under-gate channel region, an impurity of the same conductivity type as said channel region.

12. A non-volatile semiconductor memory according to claim 1 wherein:

said anisotropic resistance is an offset region formed by implanting, between said source of said transistor and said channel region, an impurity of the same conductivity type as said channel region.

6. A non-volatile semiconductor memory according to claim wherein:

drains of each of pairs of memory cells in adjacent relationship of said memory cells are connected to a common bitline;

said pairs of memory cells are placed in checkerboard arrangement to form an array structure;

two wordlines are arranged to a single sourceline, and sources of memory cells, connected to said wordlines located next to said source line, are connected to said source line.

7. A non-volatile semiconductor memory cell according to claim 6 further comprising:

a plurality of sense amplifiers, each said sense amplifier requiring a reference electric potential;

a plurality of reference dummy cells, each said reference dummy cell being arranged in each said bitline;

wherein;

said reference electric potential is generated in one of two adjoining bitlines.

8. A method of driving a non-volatile semiconductor memory;

said non-volatile semiconductor memory comprising;

an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain;

a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array;

a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array;

a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array;

a row decoder circuit for selecting among said plurality of wordlines;

a column decoder circuit for selecting among said plurality of bitlines;

a source decoder circuit for selecting among said plurality of sourcelines;

a plurality of anisotropic resistance sections;

wherein;

each said anisotropic resistance section is arranged in a path from a said bitline to a said sourceline through a said transistor;

each said anisotropic resistance section has voltage-current properties which are different for different levels of voltages applied across said anisotropic resistance section;

each said anisotropic resistance section has a forward direction in which a current flows therethrough with lesser resistance and a reverse direction in which a current flows therethrough with greater resistance;

said drive method comprising the steps of;

selecting, from among said plurality of bitlines, a bitline associated with a memory cell to be read by means of said column decoder circuit;

selecting, from among said plurality of sourcelines, a sourceline associated with said memory cell by means of said source decoder circuit;

setting the electric potential of said selected bitline and the electric potential of said selected sourceline such that the electric potential relationship of said selected bitline versus said selected sourceline agrees with said forwarding direction of said anisotropic resistance section, and setting the higher of said selected bitline'"'"'s electric potential and said selected sourceline'"'"'s electric potential as a reading electric potential;

setting the electric potential of deselected sourcelines to an electric potential level above the lower of said selected bitline'"'"'s electric potential and said selected sourceline'"'"'s electric potential but below said reading electric potential.

9. The method according to claim 8 wherein:

said non-volatile semiconductor memory further comprises;

a plurality of sense amplifiers, each of said sense amplifiers requiring a reference electric potential;

a plurality of reference dummy cells, each of said reference dummy cell being arranged in a said bitline;

wherein;

said reference electric potential is generated in one of two adjoining bitlines;

said drive method further comprising the steps of;

selecting, from among said dummy memory cells, a dummy memory cell connected to a bitline located next to said selected bitline by means of said column decoder circuit;

bringing the electric potential of a deselected bitline located next to said selected bitline to the same electric potential level as the electric potential of said selected bitline;

setting the electric potential of a sourceline connected to said selected dummy memory cell such that the electric potential relationship of a bitline connected to said selected dummy cell with said sourceline agrees with a forward direction of an anisotropic resistance section of said selected dummy cell;

generating said reference electric potential in said bitline next to said selected bitline.

10. The method according to claim 8 wherein:

all of said plurality of wordlines are set to a ground level when reading said memory cell.

11. A method of driving a non-volatile semiconductor memory;

said non-volatile semiconductor memory comprising;

an array of non-volatile memory cells arranged in columns and rows, wherein each said non-volatile memory cell has a transistor and a capacitance section, said transistor being composed of, at least, a gate, a source, and a drain;

a plurality of wordlines, wherein each said wordline is connected to each of said gates in a row of said memory cell array;

a plurality of bitlines, wherein each said bitline is connected to each of said drains in a column of said memory cell array;

a plurality of sourcelines, wherein each said sourceline is connected to each of said sources in a row of said memory cell array;

a row decoder circuit for selecting among said plurality of wordlines;

a column decoder circuit for selecting among said plurality of bitlines;

a source decoder circuit for selecting among said plurality of sourcelines;

a plurality of anisotropic resistance sections;

wherein;

each said anisotropic resistance section is arranged in a path from a said bitline to a said sourceline through a said transistor;

each said anisotropic resistance section has voltage-current properties which are different for different levels of voltages applied across said anisotropic resistance section;

each said anisotropic resistance section has a forward direction in which a current flows therethrough with lesser resistance and a reverse direction in which a current flows therethrough with greater resistance

wherein;

said forward direction of said anisotropic resistance section is formed such that voltage on the bitline side is greater than voltage on the sourceline side;

said drive method comprising the steps of;

bringing an erased memory cell to having a negative threshold voltage;

selecting, from among said plurality of bitlines, a bitline associated with a memory cell to be read by means of said column decoder circuit;

selecting, from among said plurality of sourcelines, a sourceline associated with said memory cell by means of said source decoder circuit;

bringing the electric potential of all of said wordlines to a ground level;

increasing the electric potential of said selected bitline;

bringing the electric potential of said selected sourceline to said ground level;

bringing the electric potential of deselected bitlines to said ground level;

passing an electric current between said selected bit line and said selected sourceline thereby to generate hot electrons for increasing said memory cell'"'"'s threshold voltage.