Neural network processor including systolic array of two-dimensional layers

• US 5,627,943 A
• Filed: 10/13/1995
• Issued: 05/06/1997
• Est. Priority Date: 02/17/1993
• Status: Expired due to Term

• Current Assignee: Kawasaki Microelectronics Incorporated (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated), Texas A&M University System
• Inventors: Sanchez-Sinencio, Edgar, Yoneda, Hideki
• Primary Examiner(s): Hafiz, Tariq R.
• Application Number:
  US08/542,832
• Time in Patent Office: 571 Days
• Field of Search: 382/155-159, 395/20-27
• US Class Current: 706/31
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06V 10/454 Integrating the filters into a hierarchical structure, e.g. convolutional neural networks [CNN]
• CPC Class Codes: G06V 10/955 using specific electronic processors

Abstract

The invention provides a pattern recognition processing apparatus and a technique for realizing a neural network of a complex structure within the processing apparatus. The apparatus includes a neural network having two-dimensional layers connected to form a feed-forward systolic array. Each two dimensional layer includes a feature extraction layer connected with a positional error absorbing layer. A host system provides inputs to the network. Each layer within the network includes processing elements such as a MOS analog circuit that receives input voltage signals and provides output voltage signals.

Claims

1. A pattern recognition processing apparatus, comprising:

a neural network connected to form a feed-forward systolic array, said feed-forward systolic array comprising two dimensional layers of neural processing elements, each two-dimensional layer comprising;

a feature extraction layer, and

a positional error absorbing layer connected to said feature extraction layer with said extraction and absorbing layers performing identical computational operations; and

a host system providing inputs to said network.

2. The apparatus of claim 1 wherein each layer includes at least one analog processing element, comprising:

first analog multipliers connected receive voltage inputs and constructed to form a first summed output;

second analog multipliers connected receive voltage inputs and constructed to form a second summed output; and

an analog divider connected to receive the first and second summed outputs and constructed to produce a quotient voltage output therefrom.

3. The apparatus of claim 2 wherein said analog processing elements are connected locally.

4. The apparatus of claim 2 further comprising analog pipeline coefficient storage units connected to said first and second analog multipliers.

5. The apparatus of claim 1 wherein said neural network is connected in accordance with a projection vector and a scheduling vector for maximizing processing element utilization and network processing speed.

6. The apparatus of claim 1 wherein said neural network forms a part of a Neocognitron.

7. The apparatus of claim 1 wherein each two dimensional layer comprises neurons and said neurons of each layer are connected only to neighboring neurons of a previous layer.

8. The apparatus of claim 7 wherein the previous layer is a next immediate preceding layer.