Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture

• US 5,627,976 A
• Filed: 03/20/1995
• Issued: 05/06/1997
• Est. Priority Date: 08/23/1991
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ho, Allen P., McFarland, Harold L.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/407,309
• Time in Patent Office: 778 Days
• Field of Search: 395/308, 395/280, 395/306, 395/287, 395/200.01, 395/200.15, 395/285, 395/290, 395/293, 370/85.1, 370/85.9
• US Class Current: 710/309
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4031 with arbitration

Abstract

A dual-bus architecture that includes a high-speed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as a master for both the NexBus and the AB. While it would be possible to have the adapter always request the AB (which also requires the NexBus), that would slow down NexBus operations to the bandwidth of the AB. This problem is avoided by providing two request lines for each adapter, -NREQ (NexBus only) and -AREQ (both buses), having the adapter normally assert -NREQ first. However, if the addressed device is on the AB, the ABI automatically detects this fact and attempts to do a crossing transfer to the AB, even though the request was for the NexBus only. If the ABI is unable to do the crossing transfer because the AB was busy, the ABI automatically causes the NexBus adapter to retry, the request using the -AREQ line. Thus the slower AB is only accessed when actually necessary.

Claims

1. A method of communicating data between devices in a computer system, the method comprising:

providing a bidirectional first bus, said first bus having an architecture wherein a transfer initiated on said first bus includes an address signifying a device with which communication is to be established, said architecture having a bus control signal selectively indicating that the transfer is claimed by a device addressed by said address;

providing a bidirectional second bus;

providing selective bidirectional coupling between said first and second buses;

coupling a bus master to said first bus;

coupling a slave to a selected one of said first and second buses;

storing bus configuration data for a plurality of address regions, at least some of said configuration data associating at least one of said address regions with said first bus;

initiating a particular transfer on said first bus, said particular transfer being initiated by said bus master and including a particular address;

determining whether said particular address corresponds to one of said address regions associated with said first bus; and

if not, enabling a crossing transfer from said first bus to said second bus without waiting for assertion of said bus control signal.

2. The method of claim 1, wherein said architecture of said first bus supports write transfers and read transfers, and further comprising:

signalling on said second bus during at least part of said crossing transfer whether said particular transfer is a write transfer or a read transfer;

coupling said particular address from said first bus to said second bus over at least part of said selective bidirectional coupling during at least part of said crossing transfer; and

coupling data from said first bus to said second bus, and from said second bus to said first bus, for write transfers and read transfers, respectively, said data being coupled over at least part of said selective bidirectional coupling during at least part of said crossing transfer.

3. The method of claim 1, wherein a third bus is disposed between said first and second buses.

4. The method of claim 3, wherein:

said second bus is an industry standard peripheral bus;

said third bus is a local bus; and

said selective bidirectional coupling between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

5. The method of claim 3, wherein:

said second bus is an industry standard peripheral bus selected from the group consisting of MCA, EISA, and ISA;

said third bus is a local bus selected from the group consisting of the 80386 processor local bus, and the 80486 processor local bus; and

said selective bidirectional coupling between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

6. The method of claim 1, wherein each address region resides within one of a plurality of address spaces, said address spaces including a memory address space and an I/O address space.

7. The method of claim 6, wherein said particular address is associated with said memory address space.

8. The method of claim 6, wherein said particular address is associated with said I/O address space.

9. The method of claim 1, wherein said second bus has an architecture that does not require a slave on said second bus to give an indication on said second bus when said slave on said second bus responds to said address.

10. The method of claim 1, wherein the architecture of said first bus has a multimaster arbitration protocol, and further comprising storing said particular bus transfer, to permit other operations on said first bus while said crossing transfer to said second bus is completed.

11. The method of claim 10, wherein said second bus has an architecture that does not require a slave on said second bus to give an indication on said second bus when said slave on said second bus responds to said address.

12. The method of claim 1, wherein at least some of said address regions have different block sizes.

13. The method of claim 1, wherein said storing step comprises storing said bus configuration data in a map RAM.

14. A method of communicating data between devices in a computer system, the method comprising the steps of:

providing a bidirectional first bus having a first architecture that supports coupling to a first bus master that initiates a first bus transfer, said first bus transfer including a first address signifying a slave with which communication is to be established, said first architecture having a first bus control signal selectively indicating said first bus transfer is claimed by a device addressed by said first address;

providing a bidirectional second bus having a second architecture that supports coupling to a second bus master that initiates a second bus transfer including a second address, said second address signifying a slave with which communication is to be established;

providing selective bidirectional coupling between said first and second buses;

coupling said first bus master to said first bus;

coupling said second bus master to said second bus;

coupling a slave to a selected one of said first and second buses;

storing bus configuration data for a plurality of address regions, at least some of said configuration data associating at least one of said address regions with said first bus;

enabling a first type of crossing transfer from said first bus to said second bus if said first bus master initiates a first bus transfer including a particular first address, and if said first bus control signal is not asserted within a predefined waiting period after said first bus master initiates said first bus transfer; and

enabling a second type of crossing transfer from said second bus to said first bus if said second bus master initiates a second bus transfer including a particular second address, and if said particular second address of said second bus transfer corresponds to one of said address regions associated with said first bus.

16. The method of claim 14, wherein a third bus is disposed between said first and second buses.

17. The method of claim 16, wherein:

said second bus is an industry standard peripheral bus;

said third bus is a local bus; and

said selective bidirectional coupling between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

18. The method of claim 16, wherein:

said second bus is an industry standard peripheral bus selected from the group consisting of MCA, EISA, and ISA;

said third bus is a local bus selected from the group consisting of the 80386 processor local bus, and the 80486 processor local bus; and

said selective bidirectional coupling between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

19. The method of claim 14, wherein each address region resides within one of a plurality of address spaces, said address spaces including a memory address space and an I/O address space.

20. The method of claim 19, wherein said particular address is associated with said memory address space.

21. The method of claim 19, wherein said particular address is associated with said I/O address space.

22. The method of claim 14, wherein at least some of said address regions have different block sizes.

23. The method of claim 14, wherein said first type of crossing transfer from said first bus to said second bus is enabled without waiting for assertion of said first bus control signal if said particular first address of said first bus transfer does not correspond to one of said address regions associated with said first bus.

24. The method of claim 14, wherein the computer system includes I/O, conventional memory, and extended memory, and said address regions include separate address regions for said I/O, said conventional memory, and said extended memory.

25. The method of claim 14, wherein said storing step comprises storing said bus configuration data in a map RAM.

26. The method of claim 14, wherein the architecture of said first bus has a multimaster arbitration protocol, and further comprising storing said first bus transfer, to permit other operations on said first bus while said first type of crossing transfer from said first bus to said second bus is completed.

27. A method of communicating data between devices in a computer system, the method comprising:

providing a bidirectional first bus;

providing a bidirectional second bus having a second architecture that supports coupling to a bus master that initiates a bus transfer including an address, said address signifying a slave with which communication is to be established;

coupling said bus master to said second bus;

coupling said slave to a selected one of said first and second buses;

storing bus configuration data for a plurality of address regions, at least some of said configuration data associating at least one of said address regions with said first bus, said address regions including explicit memory ranges corresponding to video memory and BIOS extensions; and

enabling a crossing transfer from said second bus to said first bus if said bus master initiates said bus transfer including a particular address, and if said particular address of said bus transfer corresponds to one of said address regions associated with said first bus.

15. The method of claim 28, wherein:

said architecture of said first and second buses support write transfers and read transfers;

said first type of crossing transfer includes signalling on said second bus during at least part of said first type of crossing transfer whether said first type of crossing transfer is a write transfer or a read transfer;

said first type of crossing transfer includes coupling said particular address from said first bus to said second bus;

said first type of crossing transfer further includes coupling data from said first bus to said second bus, and from said second bus to said first bus, for write transfers and read transfers, respectively;

said second type of crossing transfer includes signalling on said first bus during at least part of said second type of crossing transfer whether said second type of crossing transfer is a write transfer or a read transfer;

said second type of crossing transfer includes coupling said particular second address from said second bus to said first bus; and

said second type of crossing transfer further includes coupling data from said first bus to said second bus, and from said second bus to said first bus, for read transfers and write transfers, respectively.

28. The method of claim 27, wherein:

said architecture of said second bus supports write transfers and read transfers;

said crossing transfer includes signalling on said first bus during at least part of said crossing transfer whether said second type of crossing transfer is a write transfer or a read transfer;

said crossing transfer includes coupling said particular address from said second bus to said first bus; and

said crossing transfer further includes coupling data from said first bus to said second bus, and from said second bus to said first bus, for read transfers and write transfers, respectively.

29. The method of claim 27, wherein a third bus is disposed between said first and second buses.

30. The method of claim 29, wherein:

said second bus is an industry standard peripheral bus;

said third bus is a local bus; and

an I/O chip set provides selective coupling between said industry standard peripheral bus and said local bus.

31. The method of claim 29, wherein:

said second bus is an industry standard peripheral bus selected from the group consisting of MCA, EISA, and ISA;

said third bus is a local bus selected from the group consisting of the 80386 processor local bus, and the 80486 processor local bus; and

an I/O chip set provides selective coupling between said industry standard peripheral bus and said local bus.

32. The method of claim 27, wherein each address region resides within one of a plurality of address spaces, said address spaces including a memory address space and an I/O address space.

33. The method of claim 32, wherein said particular address is associated with said memory address space.

34. The method of claim 32, wherein said particular address is associated with said I/O address space.

35. The method of claim 27, wherein the computer system includes I/O, conventional memory, and extended memory, and said address regions include separate address regions for said I/O, said conventional memory, and said extended memory.

36. The method of claim 27, wherein at least some of said address regions have different block sizes.

37. The method of claim 27, wherein said storing step comprises storing said bus configuration data in a map RAM.

38. A method of maximizing the effective bandwidth in a dual-bus architecture computer, said method comprising:

providing a bidirectional first bus;

providing a bidirectional second bus;

providing selective coupling between said first and second buses;

providing a CPU coupled to said first bus, said CPU including a microprocessor and cache memory, said CPU being capable of initiating a bus transfer on said first bus;

providing an I/O device, said I/O device being capable of responding as a slave at a particular address, said particular address being within a first address region, said I/O device being a selected one of a first bus type or a second bus type, said first and second bus type I/O devices being respectively designed physically and electrically for respectively associated use on said first bus and said second bus;

installing said I/O device of said selected type on said respectively associated one of said first or second buses;

storing first bus configuration data for a plurality of address regions to permit said address regions to be associated with said first bus, said address regions including said first address region,

wherein said configuration data associates said first address region with said first bus, if said I/O device of said selected type is installed on said first bus, and

wherein said configuration data does not associate said first address region with said first bus, if said I/O device of said selected type is installed on said second bus;

providing a program, said program being in binary object code compatible with said CPU, said program being independent of said selected type of I/O device, said program including a reference to said I/O device as a slave having said particular address;

running said program on said CPU, said CPU initiating a transfer as a master on said first bus in accordance with said running program, said transfer referencing said I/O device as a slave having said particular address;

maintaining said first and second buses uncoupled during said bus transfer on said first bus, if said stored configuration data associates said first address region with said first bus; and

performing a crossing transfer from said first bus to said second bus during said bus transfer on said first bus, if said configuration data does not associate said first address region with said first bus.

39. The method of claim 38, wherein:

said first bus has an architecture that requires a slave on said first bus to give an indication on said first bus when said slave on said first bus responds to said address; and

said second bus has an architecture that does not require a slave on said second bus to give an indication on said second bus when said slave on said second bus responds to said address.

40. The method of claim 39, wherein:

said architecture of said first bus supports write transfers and read transfers;

said crossing transfer includes signalling on said second bus during at least part of said crossing transfer whether said crossing transfer is a write transfer or a read transfer;

said crossing transfer includes coupling said particular address from said first bus to said second bus; and

said crossing transfer further includes coupling data from said first bus to said second bus, and from said second bus to said first bus, for write transfers and read transfers, respectively.

41. The method of claim 40, wherein:

said particular address of said I/O device is compatible with the industry standard PC/AT architecture;

said microprocessor is compatible with the Intel 80386 architecture;

said second bus is the ISA bus, said second bus supporting I/O devices that are typically coupled to the expansion bus in a PC;

said first bus has a multimaster arbitration protocol;

said first bus is much faster than said second bus; and

said first bus supports high-speed I/O devices that are faster or wider versions of said I/O devices typically coupled to said second bus.

42. The method of claim 41, wherein said I/O device is a controller selected from the group consisting of a programmable interrupt controller, a graphics controller, a disk controller, and a network controller.

43. The method of claim 41, wherein:

each address region resides within one of a plurality of address spaces; and

said address spaces include a memory address space and an I/O address space.

44. The method of claim 43, wherein said particular address is associated with said memory address space.

45. The method of claim 43, wherein said particular address is associated with said I/O address space.

46. The method of claim 38, wherein a third bus is used intermediate between said first bus and said second bus.

47. The method of claim 46, wherein:

said second bus is an industry standard peripheral bus;

said third bus is a local bus; and

said selective coupling between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

48. The method of claim 46, wherein:

said second bus is an industry standard peripheral bus selected from the group consisting of MCA, EISA, and ISA;

said third bus is a local bus selected from the group consisting of the 80386 processor local bus, and the 80486 processor local bus; and

said selective coupling between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

49. A computer system comprising:

a bidirectional first bus having an architecture that supports a bus transfer including an address, said architecture having a bus control signal selectively indicating said bus transfer is claimed by a device addressed by said address;

a bidirectional second bus;

a bus master coupled to said first bus, said bus master having logic for placing said address of said bus transfer on said first bus signifying a slave with which communication is to be established;

a slave coupled to a selected one of said first and second buses;

bidirectional first bus interface logic coupled to said first bus;

bidirectional second bus interface logic coupled to said second bus;

at least one path selectively coupled between said first bus and said second bus, said path including said first bus interface logic and said second bus interface logic;

address mapping logic having programmable storage for first bus configuration data for a plurality of address regions to permit said address regions to be associated with said first bus; and

control logic means, coupled to said first and second bus interface logic and to said address mapping logic, said control logic means being responsive to said address, for enabling a crossing transfer from said first bus to said second bus without waiting for assertion of said first bus control signal if said address of said first bus transfer is not mapped to one of said address regions that is associated with said first bus.

50. The computer system of claim 49, wherein:

said architecture of said first bus supports write transfers and read transfers;

whether said crossing transfer is a write transfer or a read transfer is signaled on said second bus during at least part of said crossing transfer;

said address is coupled from said first bus to said second bus, said address being coupled over at least part of said at least one path during at least part of said crossing transfer; and

data is coupled from said first bus to said second bus, and from said second bus to said first bus, for write transfers and read transfers, respectively, said data being coupled over at least part of said at least one path during at least part of said crossing transfer.

51. The computer system of claim 49, wherein a third bus is used intermediate between said first bus and said second bus.

52. The computer system of claim 51, wherein:

said second bus is an industry standard peripheral bus;

said third bus is a local bus; and

said selectively coupled path between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

53. The computer system of claim 51, wherein:

said second bus is an industry standard peripheral bus selected from the group consisting of MCA, EISA, and ISA;

said third bus is a local bus selected from the group consisting of the 80386 processor local bus, and the 80486 processor local bus; and

said selectively coupled path between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

54. The computer system of claim 51, wherein each address region resides within one of a plurality of address spaces, said address spaces including a memory address space and an I/O address space.

55. The computer system of claim 54, wherein said address is associated with said memory address space.

56. The computer system of claim 54, wherein said address is associated with said I/O address space.

57. The computer system of claim 49, wherein said second bus has an architecture that does not require a slave on said second bus to give an indication on said second bus when said slave on said second bus responds to said address.

58. The computer system of claim 49, wherein the architecture of said first bus has a multimaster arbitration protocol, and further comprising a buffer, coupled to said path, for storing said first bus transfer, to permit other operations on said first bus while said crossing transfer to said second bus is completed.

59. The computer system of claim 49, wherein said programmable storage for first bus configuration data is a map RAM.

60. A bus interface unit for a computer system having at least a first bus and a second bus, wherein the architecture of said first bus has a multimaster arbitration protocol and supports coupling to a bus master for generating a bus transfer, said transfer including an address, said architecture having a bus control signal selectively indicating said bus transfer is claimed by a device addressed by said address, said bus interface unit comprising:

bidirectional first bus interface logic coupled to said first bus;

bidirectional second bus interface logic coupled to said second bus;

at least one path selectively coupled between said first bus and said second bus, said path including said first bus interface logic and said second bus interface logic;

control logic means, coupled to said first and second bus interface logic, for enabling a crossing transfer from said first bus to said second bus over said path if said bus control signal is not asserted within a predefined waiting period after said bus master initiates said bus transfer; and

a buffer, coupled to said path, for storing said first bus transfer, to permit other operations on said first bus while said crossing transfer to said second bus is completed.

61. The bus interface unit of claim 60, wherein:

said architecture of said first bus supports write transfers and read transfers;

whether said crossing transfer is a write transfer or a read transfer is signaled on said second bus during at least part of said crossing transfer;

said address is coupled from said first bus to said second bus, said address being coupled over at least part of said at least one path during at least part of said crossing transfer; and

data is coupled from said first bus to said second bus, and from said second bus to said first bus, for write transfers and read transfers, respectively, said data being coupled over at least part of said at least one path during at least part of said crossing transfer.

62. The bus interface unit of claim 60, wherein a third bus is used intermediate between said first bus and said second bus.

63. The bus interface unit of claim 62, wherein:

said second bus is an industry standard peripheral bus;

said third bus is a local bus; and

said selectively coupled path between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

64. The bus interface unit of claim 62, wherein:

said second bus is an industry standard peripheral bus selected from the group consisting of MCA, EISA, and ISA;

said third bus is a local bus selected from the group consisting of the 80386 processor local bus, and the 80486 processor local bus; and

said selectively coupled path between said first and second buses includes an I/O chip set that provides selective coupling between said industry standard peripheral bus and said local bus.

65. The bus interface unit of claim 62, wherein each address region resides within one of a plurality of address spaces, said address spaces including a memory address space and an I/O address space.

66. The bus interface unit of claim 65, wherein said address is associated with said memory address space.

67. The bus interface unit of claim 65, wherein said address is associated with said I/O address space.

68. The bus interface unit of claim 60, wherein said second bus has an architecture that does not require a slave on said second bus to give an indication on said second bus when said slave on said second bus responds to said address.