Microcomputer with programmable ROM

• US 5,628,022 A
• Filed: 06/01/1994
• Issued: 05/06/1997
• Est. Priority Date: 06/04/1993
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ueno, Masahiro, Ono, Kenichi, Yamamoto, Toshitaka
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): Darbe, Valerie
• Application Number:
  US08/252,358
• Time in Patent Office: 1,070 Days
• Field of Search: 395/800, 395/430, 395/492, 395/497.04, 395/421.01, 364/DIG. 1, 364/DIG. 2
• US Class Current: 712/37
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70

Abstract

In a microcomputer with a programmable ROM, there is provided an external pin at which a mode select signal is entered so as to select one of three modes, including a MCU mode in which an application system is controlled by an application program which has been stored in the programmable ROM, a PROM mode in which the application program is written into the programmable ROM, and an inline mode in which predetermined data is written to a part of the programmable ROM with the microcomputer mounted on a user system.

Claims

1. A microcomputer having a programmable ROM, said microcomputer comprising:

a programmable ROM;

an external pin, connected to said programmable ROM, to which a mode select signal is supplied; and

control means, connected to said external pin, responsive to said mode select signal for controlling said microcomputer to operate in one of three modes, including an MCU mode in which an application system is controlled by an application program which is stored in said programmable ROM, a PROM mode in which said application program is written to said programmable ROM, and an inline mode in which predetermined data is written to a part of said programmable ROM while said microcomputer is mounted on a user system including all components of an application system,

wherein said control means comprises at least an inline mode interface which includes a multiplexer for setting a part of a PROM address bus to a high level and another part of said PROM address bus to a low level in said inline mode.

2. A microcomputer having a programmable ROM according to claim 1, wherein said inline mode interface comprises a serial interface for transferring a PROM address and data between a PROM writer and said PROM incorporated in said microcomputer.

3. A microcomputer with a programmable ROM according to claim 1, wherein at least some of a plurality of pins for interface signals transferred between said inline interface and said PROM write operate as LCD driver/controller signal pins.

4. A system using a microcomputer incorporating a PROM, have a first area for storing a dummy constant and a dummy operational coefficient for controlling said system, a second area for storing a real constant and a real operational coefficient obtained after testing system performance by using said dummy constant and said dummy operational coefficient, and a third area for storing a flag for indicating that said real constant and said real operational coefficient have been stored in said second area.

5. A system according to claim 4, wherein said second area and said third area are set to an inline mode access area in said PROM.

6. A single-chip microcomputer comprising:

a central processing unit;

a programmable ROM for storing programs to be run by said central processing unit;

a plurality of external pins for effecting input/output of signals;

a MCU interface connected between said central processing unit and said plurality of external pins;

a PROM interface connected between said programmable ROM and said plurality of external pins in parallel with said MCU interface;

a first external mode select pin connected to supply a first mode select signal to select either said MCU interface or PROM interface for operation to connect said central processing unit to said plurality of external pins;

an in-line interface connected between said programmable ROM and said plurality of external pins, and including said PROM interface and a multiplexer for setting a part of PROM address lines to a predetermined level; and

a second external mode select pin connected to supply a second mode select signal to control the operation of said in-line interface to provide access via said plurality of external pins to only a predetermined part of said programmable ROM.

7. A single-chip microcomputer according to claim 6, wherein a plurality of address lines and a data line are connected between said programmable ROM and said PROM interface, and wherein said multiplexer is connected to at least some of said address lines.

8. A single-chip microcomputer according to claim 6, wherein a plurality of address lines and a data line are connected between said programmable ROM and said PROM interface, and wherein said in-line interface includes:

a data shift register connected to receive data from an external pin; and

an address shift register connected to receive addresses from an external pin;

wherein said multiplexer is provided, responsive to said second mode select signal, for setting a first part of said address lines to a high level, for setting a second part of said address lines to a low level, for selectively connecting the remainder of said address line to said address shift register and for selectively connecting said data lines to said data shift register.

9. A single-chip microcomputer according to claim 8, wherein said data shift register and said address shift register are connected to the same external pin, said microcomputer further including a controller, disposed in parallel between said data shift register and said address shift register and said same external pin, responsive to clock signals for controlling the operation of said data shift register and said address shift register.