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Synthesizer receiver

  • US 5,628,061 A
  • Filed: 01/17/1995
  • Issued: 05/06/1997
  • Est. Priority Date: 01/24/1994
  • Status: Expired due to Fees
First Claim
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1. A synthesizer receiver having a clock circuit for keeping a reference time, a display for displaying a local time for a local area having a predetermined time difference relationship to the reference time kept by the clock circuit, and a PLL in which a receiving signal is frequency-converted based on an output signal of the PLL, and a receiving frequency is changed by changing a frequency dividing ratio of a variable frequency dividing circuit of the PLL, comprising:

  • a table for storing data of names of areas, data of respective time differences between respective local times of the areas and the reference time, and data of respective frequency intervals, each area having a corresponding frequency interval to be added/subtracted from a first receiving frequency to effect a change to a second receiving frequency adjacent to the first receiving frequency,wherein the local time displayed on the display is determined by adding a time difference of the local area which is stored in the table to the reference time, and a variation amount of the frequency dividing ratio is set in accordance with a frequency interval corresponding to the local area.

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