Plasma enhanced chemical vapor reactor with shaped electrodes

• US 5,628,869 A
• Filed: 05/09/1994
• Issued: 05/13/1997
• Est. Priority Date: 05/09/1994
• Status: Expired due to Term

• Current Assignee: LSI Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Mallon, Thomas G.
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): ALANKO, ANITA KAREN
• Application Number:
  US08/239,987
• Time in Patent Office: 1,100 Days
• Field of Search: 156/345 P, 156/643.1, 217/71, 118/723 E, 427/569
• US Class Current: 438/694
• CPC Class Codes: C23C 16/509 using internal electrodes
• CPC Class Codes: C23C 16/52 Controlling or regulating the coating process C23C16/45557, C23C16/279 take precedence
• CPC Class Codes: H01J 37/32009 Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources plasma generation in general H05H1/24
• CPC Class Codes: H01J 37/32541 Shape
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
• CPC Class Codes: Y10T 428/24917 including metal layer
• CPC Class Codes: Y10T 428/24926 including ceramic, glass, porcelain or quartz layer
• CPC Class Codes: Y10T 428/2495 Thickness [relative or absolute]

Abstract

A semiconductor integrated circuit is made by a process including the formation on a surface of a semiconductor integrated circuit processing wafer of a layer of material applied to the wafer by plasma enhanced chemical vapor deposition (PECVD). The layer of material may include plural sub-layers, the thicknesses of which are additive to result in the thickness of the layer of material itself. The sub-layers of material may have non-uniform thicknesses across a dimension of the processing wafer because of compromises in the process which are necessary to control various parameters of the material layer other than its thickness. These non-uniformities of thickness of the sub-layers may be controlled to offset one another so that the resulting layer of material has a substantially uniform thickness across the dimension of the processing wafer. A method, and apparatus for practicing the method, are set forth along with an explanation of how particular geometric factors of electrodes used in the PECVD process affect the resulting thickness non-uniformities. The thickness non-uniformities of the sub-layers may also be largely abated by use of the invention in a predictive-corrective fashion. A similar predictive-corrective method and resulting apparatus is set forth for gas plasma etching of an existing layer of material on a semiconductor integrated circuit processing wafer.

Claims

1. A method of plasma processing a semiconductor integrated circuit processing wafer, comprising the steps of:

providing a semiconductor integrated circuit processing wafer with a surface carrying a layer of material to be plasma etched;

providing a passive electrode;

providing a feed electrode which defines with the passive electrode a gap;

disposing the processing wafer in the gap;

determining an anticipated material etching profile of non-uniformity of the layer of material to be plasma etched;

reconfiguring an active surface of the feed electrode to be non-complementary to the passive electrode and at the active surface to define a profile complementary to or like the anticipated material etching profile of non-uniformity; and

using the reconfigured feed electrode, etching the material layer more uniformly.

2. A method of plasma processing a semiconductor integrated circuit processing wafer, comprising the steps of:

providing a semiconductor integrated circuit processing wafer with a surface carrying a layer of material to be plasma etched or to which a layer of material is to be applied by plasma enhanced chemical vapor deposition (PECVD);

providing a passive electrode;

providing a feed electrode which defines with the passive electrode a gap;

disposing the processing wafer in the gap;

determining an anticipated material deposition profile of non-uniformity of the layer of material to be applied by PECVD;

reconfiguring an active surface of the feed electrode to be non-complementary to the passive electrode and at the active surface to define a profile complementary to or like the anticipated material deposition profile of non-uniformity; and

using the reconfigured feed electrode, applying the PECVD material layer with a more uniform thickness.

3. A method of making a semiconductor integrated circuit, comprising the steps of:

providing a semiconductor integrated circuit processing wafer including a substrate;

using plasma enhanced chemical vapor deposition (PECVD), forming a first material layer on the substrate, which material layer has a non-uniformity of material thickness over a dimension of the wafer;

determining an anticipated non-uniformity of material thickness over the dimension of the wafer for a second material layer to be formed on the first material layer on the substrate by the PECVD, the anticipated non-uniformity of material thickness is determined based upon the non-uniformity of material thickness of the first material layer on the substrate;

reconfiguring an active feed electrode for the PECVD to complement the anticipated non-uniformity of material thickness; and

using the complementarily reconfiguring of the electrode in the PECVD, forming the second material layer, said complementary reconfiguring of the electrode abating the anticipated non-uniformity of material thickness over the dimension of the wafer.

4. A method of making a semiconductor integrated circuit, comprising the steps of:

providing a semiconductor integrated circuit processing wafer including a substrate;

with a plasma, selectively either etching an existing layer of material on the processing wafer or applying a layer of material on the processing wafer;

disposing the processing wafer upon a passive electrode;

providing an active feed electrode which with the passive electrode defines a gap;

disposing the processing wafer in the gap;

determining an anticipated thickness non-uniformity profile of the existing material layer after etching or of the material layer to be applied;

reconfiguring an active surface of the feed electrode to be non-complementary to the passive electrode and to define with the processing wafer a non-uniform spacing selectively complementary to or like the anticipated thickness non-uniformity profile of the existing material layer after etching or of the material layer to be applied; and

using the configured electrode, etching the existing material layer by plasma etching or applying the layer of material by plasma enhanced chemical vapor deposition (PECVD) with an improved uniformity of material thickness profile.

5. The method of claim 4 wherein the passive electrode is planar.