Method of repairing an integrated circuit structure

• US 5,629,137 A
• Filed: 06/07/1995
• Issued: 05/13/1997
• Est. Priority Date: 05/16/1988
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Duda, Kathleen
• Application Number:
  US08/486,526
• Time in Patent Office: 706 Days
• Field of Search: 430/5, 430/311, 430/313, 430/315, 430/317, 430/318, 430/323, 430/325, 430/30, 156/625.1, 156/643.11, 156/659.11, 250/492.2, 250/492.21, 250/492.3
• US Class Current: 430/313
• CPC Class Codes: G01R 1/06716 Elastic
• CPC Class Codes: G01R 1/06761 related to layers
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Claims

1. A method of repairing incomplete vias in a dielectric layer of an integrated circuit structure comprising the steps of:

using a plurality of probe points to probe a via location to test electrical continuity between said via location and a test location;

determining that an incomplete via is formed in the dielectric layer of the structure at said via location; and

etching away the dielectric layer at the via location.

2. The method of claim 1 further comprising the step, prior to the step of etching away the dielectric layer at said via location, of patterning a resist with an ion-beam or E-beam.

3. The method of claim 1 wherein the dielectric layer at the via location is etched away by an ion-beam.

4. A method of repairing a defective metal trace in an integrated circuit structure comprising the steps of:

using a plurality of probe points to probe the metal trace at a probe location to test electrical continuity between the probe location and a test location;

determining that the metal trace has a defective portion; and

depositing metal over the defective portion of the trace.

5. The method of claim 4 wherein the metal is deposited by an ion-beam.

6. The method of claim 4 further comprising the step, prior to the step of depositing metal, of patterning a resist layer, and wherein said metal is then deposited through the patterned resist layer.

7. A method of repairing a defect in an integrated circuit structure comprising the steps of:

probing the integrated circuit structure with a pattern of probe points,

each of said probe points having a maximum outside diameter of less than one mil;

testing electrical continuity between one of said probe points and a test location;

determining that there is a defect in the integrated circuit structure proximate to said one probe point; and

locally repairing the defect.

8. The method of claim 7 wherein the step of locally repairing the defect comprises removal of a material.

9. The method of claim 8 wherein the material is removed by an ion-beam.

10. The method of claim 8 wherein the material removed is a metal.

11. The method of claim 8 wherein the material removed is a dielectric.

12. The method of claim 7 wherein the step of locally repairing the defect comprises deposit of a material.

13. The method of claim 12 wherein the material is deposited by an ion-beam.

14. The method of claim 12 wherein the material deposited is a metal.