Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
First Claim
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1. A transistor comprising:
- a substrate region doped a first conductivity type;
a drift region overlying the substrate region and doped the first conductivity type to a lower concentration than the substrate;
a body region overlying the drift region and doped a second conductivity type;
a conductive gate electrode extending from a principal surface of the body region through the body region;
a source region doped the first conductivity type and formed in the body region, and extending to the principal surface thereof; and
a buried layer region doped the first conductivity type to a concentration greater than that of the substrate region, and extending at least in part into the drift region and adjacent the substrate region.
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Abstract
A trench DMOS transistor includes a buried layer region formed between the drain region and overlying drift region and having a doping type the same as that of the drift region and drain region. The buried layer region is more highly doped than the drain region or drift regions and is formed by e.g. implantation prior to epitaxial growth of the overlying drift region. By providing an optimized doping profile for the buried layer region, it is ensured that avalanche breakdown occurs at the buried layer region/body region. Thus drain-source on resistance is reduced because the JFET region present in prior art devices is eliminated, while device ruggedness and reliability are enhanced.
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Citations
12 Claims
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1. A transistor comprising:
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a substrate region doped a first conductivity type; a drift region overlying the substrate region and doped the first conductivity type to a lower concentration than the substrate; a body region overlying the drift region and doped a second conductivity type; a conductive gate electrode extending from a principal surface of the body region through the body region; a source region doped the first conductivity type and formed in the body region, and extending to the principal surface thereof; and a buried layer region doped the first conductivity type to a concentration greater than that of the substrate region, and extending at least in part into the drift region and adjacent the substrate region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A transistor comprising:
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a substrate region doped a first conductivity type; a drift region overlying the substrate region and doped the first conductivity type to a lower concentration than the substrate; a body region overlying the drift region and doped a second conductivity type; a conductive gate electrode extending from a principal surface of the body region through the body region; a source region doped the first conductivity type and formed in the body region, and extending to the principal surface thereof; and a buried layer region doped the first conductivity type tea concentration greater than that of the drift region, and extending at least in part into the drift region and adjacent the substrate region, wherein the buried layer region extends to within 0.5 μ
m of the body region.
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12. A transistor comprising:
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a substrate region doped a first conductivity type; a drift region overlying the substrate region and doped the first conductivity type to a lower concentration than the substrate; a body region overlying the drift region and doped a second conductivity type; a conductive gate electrode extending from a principal surface of the body region through the body region; a source region doped the first conductivity type and formed in the body region, and extending to the principal surface thereof; and a buried layer region doped the first conductivity type to a concentration greater than that of the drift region, and extending at least in part into the drift region and adjacent the substrate region, wherein a width of the buried layer region is in a range of 1 to 2 μ
m.
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Specification