Dual threshold current mode digital PWM controller

• US 5,629,610 A
• Filed: 05/08/1995
• Issued: 05/13/1997
• Est. Priority Date: 05/06/1994
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Scrocchi, Giuseppe, Pedrazzini, Giorgio, Rossi, Domenico, Cordini, Paolo
• Primary Examiner(s): Sterrett, Jeffrey L.
• Application Number:
  US08/436,947
• Time in Patent Office: 736 Days
• Field of Search: 323/282, 323/283, 323/284, 323/285, 323/299, 323/351
• US Class Current: 323/283
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence

Abstract

A fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance. The first comparator exerts an open-loop current mode control. The second comparator, establishing a second higher current threshold than the current threshold set by the first comparator, triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator. The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.

Claims

1. A method for driving a power output terminal, comprising the steps of:

(a.) sensing an input current, and accordingly

(b.) using a first open loop, activating a switching transistor when said input current falls below a first threshold, and

(c.) using a second open loop, disabling said switching transistor when said input current rises above a second threshold.

2. The method of claim 1, wherein said switching transistor is a power field effect transistor.

3. The method of claim 1, wherein said switching transistor is a power field effect transistor having one terminal thereof connected to a boosting capacitor, which is connected in a charge-pumping configuration to provide a boosted supply voltage to the gate of said power transistor.

4. A digital, current mode, PWM control circuit for an output stage comprising a sensing resistance of an input current connected in series with a power switch of the output stage, a bistable driving circuit having a clock input suitable to receive a PWM clock signal and a reset input driven by an output of a multi-input logic circuit, comprising:

at least a first comparator of the voltage on said sensing resistance having a certain threshold and an output connected to a first input of said logic circuit;

at least a second comparator of the voltage on said sensing resistance, having a threshold higher than the threshold of said first comparator and an output connected to a second input of said logic circuit;

means driven by the output of said second comparator capable of generating a logic signal for disabling said power switch for a preset period of time, fed to a third input of said logic circuit.

5. A control circuit as defined in claim 4, wherein said means comprise a bistable logic circuit having at least a reset input driven by a time counter which is activated by said disabling logic signal generated on an output of said bistable circuit.

6. A control circuit as defined in claim 5, wherein said bistable circuit is a D-type flip-flop having an input connected to a supply node, an output connected to said third input of said logic circuit, an input connected to the output of said second comparator and a reset input driven by said time counter.

7. A control circuit as defined in claim 6, wherein said time counter comprises a clock frequency divider circuit, which is enabled by the signal present on said output of said flip-flop and capable of generating a reset signal of said flip-flop, after a preset number of clock'"'"'s cycles from a transition instant of said output.

8. A control circuit as defined in claim 7, wherein the clock frequency divider circuit comprises:

a first clock frequency divider circuit generating a PWM clock frequency signal which is fed to said clock input of said driving bistable circuit;

said PWM clock signal being applied to the input of a second clock frequency divider circuit activated by the transition of said output of said flip-flop capable of generating a reset signal for said flip-flop after a preset number of cycles.

9. A control circuit as defined in claim 8, further comprising an edge detector of a transition from a low logic state to a high logic state of said output of said flip-flop and capable of generating a reset signal fed to a reset input of said clock frequency divider circuit.

10. A control circuit as defined in claim 4, wherein said driving bistable circuit is a D-type flip-flop.

11. A control circuit as defined in claim 4, wherein said multi-input logic circuit is a NOR gate.

12. A control circuit as defined in claim 4, further comprising a comparator for controlling the output voltage, which generates an overvoltage limiting logic signal applicable to a fourth input of said logic circuit.

13. A switched power output subsystem, comprising:

a switching transistor operatively connected between a first power supply terminal and a power output terminal;

at least one reactance, connected to provide a smoothed current at said output terminal;

a pulse generation circuit, operatively connected to apply pulses to a control terminal of said transistor in dependence on at least one control signal;

a first control loop which compares the current at said first power supply terminal against a first threshold and selectively activates said pulse generation circuit accordingly;

a second control loop which compares the current at said first power supply terminal against a second threshold and selectively blocks said pulse generation circuit accordingly.

14. The subsystem of claim 13, wherein said reactance comprises an inductor.

15. The subsystem of claim 13, wherein said reactance is an LC circuit.

16. The subsystem of claim 13, wherein said switching transistor is a power field effect transistor.

17. The subsystem of claim 13, wherein said switching transistor is a power field effect transistor having one terminal thereof connected to a boosting capacitor, which is connected in a charge-pumping configuration to provide a boosted supply voltage to the gate of said power transistor.

18. A switched power output subsystem, comprising:

a switching transistor operatively connected between a first power supply terminal and a power output terminal;

at least one reactance, connected to provide a smoothed current at said output terminal;

a pulse generation circuit, operatively connected to apply fixed-frequency variable-duration pulses to a control terminal of said transistor in dependence on at least one control signal;

a first control loop which compares the current at said first power supply terminal against a first threshold and selectively activates said pulse generation circuit accordingly;

a second control loop which compares the current at said first power supply terminal against a second threshold and selectively blocks said pulse generation circuit against activation by said first control loop accordingly;

a third control loop which monitors the voltage at said output terminal and selectively activates said pulse generation circuit accordingly;

wherein said first and second control loops are both open loops.

19. The subsystem of claim 18, wherein said reactance is an LC circuit.

20. The subsystem of claim 18, wherein said switching transistor is a power field effect transistor.

21. The subsystem of claim 18, wherein said switching transistor is a power field effect transistor having one terminal thereof connected to a boosting capacitor, which is connected in a charge-pumping configuration to provide a boosted supply voltage to the gate of said power transistor.

22. The subsystem of claim 18, wherein said reactance comprises an inductor.