Semiconductor wafer contact system and method for contacting a semiconductor wafer

• US 5,629,630 A
• Filed: 02/27/1995
• Issued: 05/13/1997
• Est. Priority Date: 02/27/1995
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lindsey, Scott E., Vasquez, Barbara, Williams, William M., Thompson, Patrick F.
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US08/395,127
• Time in Patent Office: 806 Days
• Field of Search: 324/72.5, 324/754, 324/765, 324/755, 324/761, 324/158.1, 324/73.1, 439/482, 439/824
• US Class Current: 324/754.13
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

A semiconductor wafer contact system includes a base substrate (13) which has an array of raised supports (18). The array of raised supports (18) are distributed in a pattern corresponding to the pattern of electrical contacts (12) on the semiconductor wafer (10), to be contacted. In between the base substrate (13) and the wafer to be contacted (10) is a flexible circuit layer (14) including an array of electrical contacts (15) having the same pattern as the contacts (12) of the wafer and the raised supports (18). The raised supports (18) provide focused and localized force, pressing the membrane test contacts (15) against the wafer electrical contacts (12).

Claims

1. A semiconductor wafer contact test system comprising:

a flexible membrane comprising a first plurality of electrical contacts; and

a support substrate pressing against the flexible membrane, the support substrate comprising a grid of raised supports, each of the first plurality of electrical contacts aligned to a separate one of the raised supports.

2. The system of claim 1, wherein the support substrate includes a compliant coating on a surface of the support substrate facing the flexible membrane.

3. The semiconductor wafer contact test system of claim 1, wherein the first plurality of electrical contacts comprises electrically conductive bumps.

4. The system of claim 1, wherein the support substrate further comprises a plurality of recesses separating the raised supports, the recesses permitting a plurality of portions of the flexible membrane to bow into the recesses.

5. The semiconductor wafer contact test system according to claim 1, wherein the semiconductor wafer contact test system tests a plurality of dice distributed in a first surface of a semiconductor wafer, each of the plurality of dice comprising a second plurality of electrical contacts, each of the second plurality of electrical contacts aligned to a separate one of the raised supports and to a separate one of the first plurality of electrical contacts.

6. A semiconductor wafer contact test system comprising:

a base including a grid of raised supports;

a compliant layer overlying the grid of raised supports; and

a removable flexible circuit layer overlying the compliant layer, the removable flexible circuit layer including a grid of electrical contacts, each of the grid of electrical contacts aligned to a different one of the grid of raised supports.

7. The system of claim 6, wherein the base comprises an etched silicon substrate.

8. The system of claim 6, wherein the base comprises a machined substrate.

9. The system of claim 6, wherein the base comprises a molded substrate.

10. The system of claim 6, wherein the compliant layer comprises polyurethane.

11. The semiconductor wafer contact test system of claim 6, wherein the base further includes a plurality of recessed regions between the raised supports, the recessed regions permitting portions of the removable flexible circuit layer to bow into the recessed regions.

12. The semiconductor wafer contact test system according to claim 6, wherein the semiconductor wafer contact test system tests a semiconductor wafer having a third grid of electrical contacts, each of the first grid of raised supports aligned to a different one of the third grid of electrical contacts.

13. A semiconductor wafer contact test system comprising:

a base including a grid of raised supports wherein the base includes a vacuum orifice;

a compliant layer overlying the grid of raised supports; and

a removable flexible circuit layer overlying the compliant layer, the removable flexible circuit layer including a grid of electrical contacts, each of the grid of raised supports aligned to a different one of the grid of electrical contacts.

14. A semiconductor wafer contact test system comprising:

a base substrate including a first array of ridges separated from one another by respective recessed regions; and

a circuit layer overlying the base substrate, the circuit layer comprising a second array of electrical contacts, each of the first array of ridges aligned to only one of the second array of electrical contacts.

15. The semiconductor wafer contact test system of claim 14, further comprising a compliant coating on the base substrate, the compliant coating located between the base substrate and the circuit layer.

16. The system of claim 14, wherein the second array of electrical contacts comprises protruding bumps.

17. The system of claim 14, wherein the first array of ridges is machined.

18. The system of claim 14, wherein the first array of ridges is etched.

19. The system of claim 14, wherein the first array of ridges is molded.

20. The system of claim 14, wherein the base substrate comprises silicon.

21. The semiconductor wafer contact test system according to claim 14, wherein the semiconductor wafer contact test system tests a semiconductor wafer comprising a third array of electrical contacts, each of the first array of ridges aligned to only one of the third array of electrical contacts.

22. A method for contacting a semiconductor wafer, the method comprising the steps of:

providing a flexible membrane comprising a first plurality of electrical contacts; and

pressing a support substrate against the flexible membrane, the support substrate comprising a grid of raised supports, each of the first plurality of electrical contacts aligned to a separate one of the raised supports.

23. The method according to claim 22 further comprising:

providing a plurality of dice distributed in a surface of the semiconductor wafer, each of the plurality of dice comprising a second plurality of electrical contacts;

aligning the second plurality of electrical contacts to the grid of raised supports and to the first plurality of electrical contacts; and

testing the plurality of dice.

24. A method of manufacturing a semiconductor device comprising:

providing a base including a grid of raised supports;

covering the grid of raised supports with a compliant layer;

providing a removable flexible circuit layer overlying the compliant layer, the removable flexible circuit layer including a grid of electrical contacts, each of the grid of electrical contacts aligned to a different one of the grid of raised supports; and

pressing the grid of raised supports towards the grid of electrical contacts.

25. The method according to claim 24, further comprising the steps of:

situating the semiconductor wafer adjacent to the removable flexible circuit layer, the semiconductor wafer including a different grid of electrical contacts, the grid of raised supports aligned to the different grid of electrical contacts;

pressing the grid of electrical contacts towards the different grid of electrical contacts; and

electrically testing the semiconductor wafer.

26. A method of contacting a semiconductor wafer, the method comprising the steps of:

providing a base substrate including a first array of ridges separated from one another by respective recessed regions;

providing a circuit layer overlying the base substrate, the circuit layer comprising a second array of electrical contacts, each of the first array of ridges aligned to only one of the second array of electrical contacts; and

pressing the first array of ridges against the second array of electrical contacts, the respective recessed regions permitting a plurality of portions of the circuit layer to bow.

27. The method according to claim 26, further comprising the steps of:

positioning the semiconductor wafer adjacent to the circuit layer, the semiconductor wafer comprising a third array of electrical contacts, the first array of ridges aligned to the third array of electrical contacts;

pressing the second array of electrical contacts towards the third array of electrical contacts;

electrically biasing the second array of electrical contacts; and

using the second array of electrical contacts to electrically test the semiconductor wafer.