Superconducting fault-tolerant programmable memory cell incorporating Josephson junctions
First Claim
Patent Images
1. A superconducting fault-tolerant programmable memory cell comprising:
- N bit lines of superconducting wires disposed in substantially parallel relation to one another;
N word lines of superconducting wires disposed in substantially parallel relation to one another, said word lines being superimposed with said bit lines and being disposed substantially orthogonally with respect to said bit lines; and
N×
N nodes of Josephson junctions, a junction being formed at each of the intersections of said bit lines and said word lines, comprising a READ array to address stored information in the form of a N-bit image.
2 Assignments
0 Petitions
Accused Products
Abstract
A superconducting fault-tolerant programmable read-only memory (SFT-PROM) cell stores information in the phases of superconducting wires in a Josephson array. The information is addressable and retrievable in a fault-tolerant manner due to the non local nature of the information stored. The coding and decoding process is content-addressable and parallel due to the multitude of interconnections, resulting in picosecond data access time. The SFT-PROM cell comprises superposed WRITE/READ arrays and a reset circuit that ensures multiple non-destructive read-out of data.
48 Citations
20 Claims
-
1. A superconducting fault-tolerant programmable memory cell comprising:
-
N bit lines of superconducting wires disposed in substantially parallel relation to one another; N word lines of superconducting wires disposed in substantially parallel relation to one another, said word lines being superimposed with said bit lines and being disposed substantially orthogonally with respect to said bit lines; and N×
N nodes of Josephson junctions, a junction being formed at each of the intersections of said bit lines and said word lines, comprising a READ array to address stored information in the form of a N-bit image. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A superconducting fault-tolerant programmable memory cell comprising:
-
N bit lines of superconducting wires disposed in substantially parallel relation to one another; N word lines of superconducting wires disposed in substantially parallel relation to one another, said word lines being superimposed with said bit lines and being disposed substantially orthogonally with respect to said bit lines; and N×
N nodes of Josephson junctions in superconducting phase, a junction being formed at each of the intersections of said bit lines and said word lines, comprising a READ array to retrieve stored information in the form of a N-bit image. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification