Diagnostic system for run-time monitoring of computer operations

• US 5,630,048 A
• Filed: 05/19/1994
• Issued: 05/13/1997
• Est. Priority Date: 05/19/1994
• Status: Expired due to Fees

• Current Assignee: Silicon Group, Inc. (Synopsys Incorporated)
• Original Assignee: Silicon Group, Inc. (Synopsys Incorporated)
• Inventors: La Joie, Leslie T., Solka, Michael B., Miller, Eugene M., Dobbs, Carl S.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US08/246,058
• Time in Patent Office: 1,090 Days
• Field of Search: 395/575, 395/182.08, 395/182.09, 395/182.1, 395/183.01, 395/183.13, 395/183.14, 395/183.15, 395/183.16, 395/183.19, 395/184.01, 395/18 0, 364/239, 364/239.1, 364/939.4, 371/67.1, 371/68.3, 371/26, 371/25.1, 371/22.4
• US Class Current: 714/25
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 11/349 for interfaces, buses
• CPC Class Codes: G06F 2201/83 the solution involving signatures

Abstract

A monitoring system is coupled to an external computer system by an interface between a data bus internal to the monitoring system and a target bus within the external computer system. Data captured by the monitoring system from the external computer system is provided in parallel to a triggering circuit and to a buffer for temporary storage, The triggering circuit identifies the occurrence of a transaction on the bus of the external computer system and generates a signal to mark a captured data block within the buffer as being characteristic of the triggering transaction. The captured data block is compared with predetermined sets of known transaction data to determine if the captured data block is consistent with the normal operation of the external computer system. A second monitoring facility is provided to perform boundary scan testing on the external computer system.

Claims

1. A monitoring system comprising:

a processing unit coupled to a data bus;

an interface between the data bus and an external computer system, said interface for coupling to a bus within the external computer system to receive signals from the bus within the external computer system and to provide signals from the external computer system directly to said data bus;

a latch, connected to said data bus for receiving and storing signals from said data bus provided from said interface, wherein said latch stores said signals at a rate at which said signals are provided on the external data bus;

a writable memory for storing a plurality of at least portions of said signal stored within said latch;

a first data path coupled to said latch, wherein said signals from the latch pass along said first data path to said writable memory;

a second data path coupled to said latch;

a trigger circuit to receive said signals provided to the interface from the external computer system along said second data path wherein said trigger circuit generates a trigger signal on the basis of a comparison between a one of said signals from said latch and a predetermined mask pattern representing a state of a bus that is diagnostic between normal, error-free operation and abnormal, incorrect operation of the external computer system, wherein said trigger signal identifies a target transaction on the bus of the external computer system; and

a filter circuit connected to said first data path and to said writable memory, said instructions from the latch passing through said filter circuit before being provided to said writable memory, wherein said filter circuit causes some of said signals from said latch to not be stored in said writable memory.

2. The monitoring system of claim 1 wherein said signals provided to said filter circuit comprise data words having a first number of data bits corresponding to a number of data bits carried in parallel on the bus in the external computer system and wherein said filter circuit causes a portion of each data word to not be stored in said writable memory.

3. The monitoring system of claim 1 wherein said trigger circuit generates said trigger signal so as to define a target time within said external computer system at which said target transaction occurred and wherein a data block stored within said writable memory includes data present on the bus of the external computer system at said target time, said data block including data present on the bus of the external computer system at a time prior to said target time and data present on the bus of the external computer system a time after said target time.

4. The monitoring system of claim 3 wherein said trigger circuit generates a tag characteristic of said one of said received signals, wherein said tag is appended to said data block.

5. A monitoring system according to claim 1, further comprising:

a second memory coupled to said writable memory through a control bus; and

a memory controller coupled to said writable memory and to said second memory, wherein said memory controller causes said writable memory to transfer a data block to said second memory upon receipt by said memory controller of said trigger signal generated by said trigger circuit.

6. The monitoring system of claim 5 wherein said second memory is disposed within said processing unit.

7. A monitoring system comprising:

a processing unit coupled to a data bus;

an interface between the data bus and an external computer system, said interface for coupling to a bus within the external computer system to receive signals from the bus within the external computer system and to provide signals from the external computer system directly to said data bus;

a latch connected to said data bus for receiving and storing signals from said data bus provided from said interface, wherein said latch stores said signals at a rate at which said signals are provided on the external data bus;

a writable memory for storing a plurality of at least portions of said signals stored within said latch;

a first data path coupled to said latch, wherein said signals from the latch pass along said first data path to said writable memory;

a second data path coupled to said latch;

a trigger circuit to receive said signals provided to the interface from the external computer system along said second data path, wherein said trigger circuit generates a trigger signal on the basis of a comparison between a one of said signals from said latch and a predetermined mask pattern representing a state of a bus that is diagnostic between normal, error-free operation and abnormal, incorrect operation of the external computer system, wherein said trigger signal identifies a target transaction on the bus of the external computer system;

a second memory coupled to said writable memory through a control bus; and

a memory controller coupled to said writable memory and to said second memory, wherein said memory controller causes said writable memory to transfer a data block to said second memory upon receipt by said memory controller of said trigger signal generated by said trigger circuit.

8. The monitoring system of claim 7 wherein said second memory is disposed within said processing unit.

9. The monitoring system of claim 7 wherein said trigger circuit generates said trigger signal so as to define a target time within said external computer system at which said target transaction occurred and wherein a data block stored within said writable memory includes data present on the bus of the external computer system at said target time, said data block including data present on the bus of the external computer system at a time prior to said target time and data present on the bus of the external computer system a time after said target time.

10. The monitoring system of claim 9 wherein said trigger circuit generates a tag characteristic of said one of said received signals, wherein said tag is appended to said data block.