Fault-tolerant computer system capable of preventing acquisition of an input/output information path by a processor in which a failure occurs

• US 5,630,053 A
• Filed: 03/22/1995
• Issued: 05/13/1997
• Est. Priority Date: 03/22/1994
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Morikawa, Takahiro
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Palys, Joseph E.
• Application Number:
  US08/408,302
• Time in Patent Office: 783 Days
• Field of Search: 395/184.01, 395/182.08, 395/182.09, 395/185.08, 395/183.07, 395/182.02, 395/182.1, 395/200.05, 395/200.11, 395/185.01
• US Class Current: 714/47.1
• CPC Class Codes: G05B 9/03 with multiple-channel loop, i.e. redundant control systems
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0796 Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2033 switching over of hardware resources
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2041 with more than one idle spare processing component

Abstract

In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths, respectively, an n-th processor is connected to an (n-1)-th processor, an (n-2)-th processor, an (n+1)-th processor, and an (n+2)-th processor, where n represents each of 1 through N, both inclusive. Coupled to the first through the N-th processor input/output information transmission paths and to a system input/output information transmission path for a controlled system, an input/output information path control device connects the system input/output information transmission path to one of the first through the N-th processor input/output information transmission paths. The n-th processor comprises an n-th central processing unit (CPU) for managing the whole of the (n-1)-th processor, an n-th failure detecting circuit for always monitoring an operation state in the (n-1)-th processor, and an n-th input/output information transmission path acquisition control circuit for directing control operation for the input/output information transmission path control device.

Claims

1. A computer system comprising:

first through N-th processors which are provided with first through N-th input/output information transmission paths, respectively, where N represents a positive integer which is not less than two, where n represents each of integers 1 through N, and where;

when n is equal to N, an (n+1)-th processor corresponds to the first processor and an (n+2)-th processor corresponds to a second processor,

when n is equal to N-1, the n+2)-th processor corresponds to the first processor,

when n is equal to N-1, an (n-1)-th processor corresponds to the N-th processor and an (n-2)-th processor corresponds to an (N-1)-th processor, and

when n is equal to 2, the (n-2)-th processor corresponds to the N-th processor; and

an input/output information transmission path control device coupled to the first through the N-th input/output information transmission paths and to a system input/output information transmission path for a controlled system, said input/output information transmission path control device configured to connect the system input/output information transmission path to one of the first through the N-th input/output information transmission paths, wherein

in n-th processor comprises;

an n-th central processing unit (CPU) connected to an n-th input/output information transmission path, said (n-1)-th processor, and said (n+1)-th processor, said n-th CPU managing the n-th processor,

an n-th failure detecting circuit connected to said (n-1)-th processor and said n-2)-th processor for monitoring an operation state in said (n-1)-th processor, and

an n-th input/output information transmission path acquisition control circuit connected to said n-th CPU, said input/output information transmission path control device, said n+1)-th processor, and said (n+2)-th processor, for directing a control operation of said input/output information transmission path control device, and wherein

said n-th CPU periodically supplies said (n+1)-th processor with an n-th periodic signal indicative of an operation state of the n-th CPU,

said n-th failure detecting circuit monitors the operation state in said (n-1)-th processor by receiving an (n-1)-th periodic signal from said (n-1)-th processor, said n-th failure detecting circuit delivering an n-th monitored result signal to said -th CPU and to an (n-2)-th input/output information transmission path acquisition control circuit in said (n-2)-th processor,

said n-th CPU supplies said n-th input/output information transmission path acquisition control circuit with an n-th input/output information transmission path acquisition request signal when said n-th CPU requires acquisition of the system input/output information transmission path,

said n-th CPU supplies, in response to the n-th monitored result signal, an n-th input/output information transmission path acquisition prohibited signal to an (n-1)-th input/output information transmission path acquisition control circuit in said (n-1)-th processor, said n-th input/output information transmission path acquisition prohibited signal indicating whether or not said n-th CPU determines that said (n-1)-th processor may acquire the system input/output information transmission path, and

said n-th input/output information transmission path acquisition control circuit receives an (n+2)-th monitored result signal, the n-th input/output information transmission path acquisition request signal, and an (n+1)-th input/output information transmission path acquisition prohibited signal,

said n-th CPU, an (n+1)-th CPU in said (n+1)-th processor, and said n-th input/output information transmission path acquisition control circuit providing a determination of whether or not the system input/output information transmission path can be acquired by the n-th processor on the basis of the (n+2)-th monitored result signal and the (n+1)-th input/output information transmission path acquisition prohibited signal,

said n-th input/output information transmission path acquisition control circuit directing, in response to the n-th input/output information transmission path acquisition request signal and in accordance with the determination, said input/output information transmission path control device to operate control of acquisition of the system input/output information transmission path.

2. A computer system as claimed in claim 1, wherein said first through said N-th input/output information transmission paths comprise first through N-th internal buses, said system input/output information transmission path comprising an outer bus, said input/output information transmission path control device comprising first through N-th bus drivers in said first through N-th processors that couples the first through the N-th internal buses with the outer bus, respectively.

3. A computer system as claimed in claim 1, wherein said first through said N-th input/output information transmission paths comprise first through N-th input/output channels, said system input/output information transmission path comprises a system input/output channel, said input/output information transmission path control device comprising an input/output control device which is provided for said first through said N-th processors in common.

4. A computer system comprising:

first through N-th processors which are provided With first through N-th input/output information transmission paths, respectively, where N represents positive integer which is not less than two, where n represents each of integers 1 through N, and where;

when n is equal to N, an (n+1)-th processor corresponds to the first processor and an (n+2)-th processor corresponds to a second processor,

when n is equal to N-1, the n+2)-th processor corresponds to the first processor,

When n is equal to 1, an n-1)-th processor corresponds to the N-th processor and an n-2))-th processor corresponds to an (N-1)-th processor, and

when n is equal to 2, the (n-2)-th processor corresponds to the N-th processor; and

an input/output information transmission path control device coupled to the first through the N-th input/output information transmission paths and to a system input/output information transmission path for a controlled system, said input/output information transmission path control device configured to connect the system input/output information transmission path to one of the first through the N-th input/output information transmission paths, wherein

an n-th processor comprises;

an n-th central processing unit (CPU) connected to an n-th input/output information transmission path, said (n-1)-th processor, and said (n+1)-th processor, said n-th CPU managing the n-th processor,

an n-th failure detecting circuit connected to said (n-1)-th processor and said (n-2)-th processor for monitoring an operation state in said (n-1)-th processor, and

an n-th input/output information transmission path acquisition control circuit connected to said n-th CPU, said input/output information transmission path control device, said (n+1)-th processor, and said (n+2)-th processor, for directing a control operation of said input/output information transmission path control device, and wherein

said n-th CPU periodically supplies said (n+1)-th processor with an n-th periodic signal indicative of an operation state of the n-th CPU,

said n-th failure detecting circuit monitors the operation state in said (n-1)-th processor by receiving an (n-1)-th periodic signal from said (n-1)-th processor, said n-th failure detecting circuit delivering an n-th monitored result signal to said n-th CPU and to an (n-2)-th input/output information transmission path acquisition control circuit in said (n-2)-th processor;

said n-th CPU supplying said n-th input/output information transmission path acquisition control circuit with an n-th input/output information transmission path acquisition request signal when said n-th CPU requires acquisition for the system input/output information transmission path, said n-th CPU supplying, in response to the n-th monitored result signal, an n-th input/output information transmission path acquisition prohibition signal to an (n-1)-th input/output information transmission path acquisition control circuit in said (n-1)-th processor, said n-th input/output information transmission path acquisition prohibition signal indicating that acquisition for the system input/output information transmission path by said (n-1)-th processor is prohibited when the n-th monitored result signal indicates that a failure occurred in said (n-1)-th processor,

said n-th input/output information transmission path acquisition control circuit receiving an (n+2)-th monitored result signal, the n-th input/output information transmission path acquisition request signal, and an (n+1)-th input/output information transmission path acquisition prohibition signal

said n-th CPU, an (n+1)-th CPU of said (n+1)-th processor, respectively, when the (n+2)-th monitored result signal indicates that a failure occurs in said (n+1)-th processor, and said n-th input/output information transmission path acquisition control circuit directing, on the basis of the n-th input/output information transmission path acquisition request signal, said input/output information transmission path control device to operate control of acquisition of the system input/output information transmission path in defiance of the (n+1)-th input/output information transmission path acquisition prohibition signal, and

when the (n+2)-th monitored result signal indicates that no failure occurred in said (n+1)-th processor, said n-th input/output information transmission path acquisition control circuit directing said input/output information transmission path control device to operate control of acquisition of the system input/output information transmission path by processing the n-th input/output information transmission path acquisition request signal in accordance with the (n+1)-th input/output information transmission path acquisition prohibition signal.

5. A computer system as claimed in claim 4, wherein said n-th failure detecting circuit produces the n-th monitored result signal having a logic one value when no failure occurs in said (n-1)-th processor, said n-th failure detecting circuit producing the n-th monitored result signal having a logic zero value when a failure occurs in said (n-1)-th processor;

said n-th CPU supplying the (n-1)-th input/output information transmission path acquisition control circuit of said (n-1)-th processor with the n-th input/output information transmission path acquisition prohibition signal having a logic one value indicating the acquisition for the system input/output information transmission path by said (n-1)-th processor when the n-th monitored result signal indicates that a failure occurs in said (n-1)-th processor;

said n-th input/output information transmission path acquisition control circuit comprising;

an n-th AND circuit, connected to the (n+2)-th failure detecting circuit of said (n+2)-th processor and the (n+1)-th CPU of said (n+1)-th processor, for carrying out an AND operation on the (n+2)-th monitored result signal and the (n+1)-th input/output information transmission path acquisition prohibition signal to produce an n-th AND'"'"'ed output signal; and

an n-th OR circuit, connected to said n-th AND circuit and said n-th CPU, for carrying out an OR operation on the n-th AND'"'"'ed output signal and the n-th input/output information transmission path acquisition request signal, said n-th OR circuit supplying said input/output information transmission path control device with an n-th OR'"'"'ed output signal to control the acquisition of the system input/output information transmission path.

6. A computer system comprising:

first through N-th processors which are provided with first through N-th input/output channels, respectively, where N represents a positive integer which is not less than two, where n represents each of integers 1 through N, and where;

When n is equal to N, an (n+1)-th processor corresponds to the first processor and an n+2)-th processor corresponds to a second processor,

When n is equal to N-1, the (n+2)-th processor corresponds to the first processor,

When n is equal to 1, an (n-1)-th processor corresponds to the N-th processor and an (n-2)-th processor corresponds to an (N-1)-th processor, add

when n is equal to 2, the (n-2)-th processor corresponds to the N-th processor; and

an input/output control device coupled to the first through the N-th input/output channels and to a system input/output channel for a controlled system, said input/output control device configured to connect the system input/output channel to one of the first through the N-th input/output channels, wherein

an n-th processor comprises;

an n-th central processing unit (CPU) connected to an n-th input/output channel, said (n-1)-th processor, and said (n+1)-th processor, said n-th CPU managing the n-th processor,

an n-th failure detecting circuit connected to said (n-1)-th processor and said (n-2)-th processor for monitoring an operation state in said (n-1)-th processor, and

an n-th input/output channel acquisition control circuit connected to said n-th CPU, said input/output control device, said (n+1)-th processor, and said (n+2)-th processor, for directing a control operation of said input/output control device, and wherein

said n-th CPU periodically supplies said (n+1)-th processor with an n-th periodic signal indicative of an operation state of the n-th CPU,

said n-th failure detecting circuit monitors the operation state in said (n-1)-th processor by receiving an (n-1)-th periodic signal from said (n-1)-th processor, said n-th failure detecting circuit delivering an n-th monitored result signal to said n-th CPU and said (n-2)-th processor,

said n-th CPU supplies said n-th input/output channel acquisition control circuit with an n-th input/output channel acquisition request signal when said n-th CPU requires acquisition of the system input/output channel,

said n-th CPU supplies an (n-1)-th input/output channel acquisition control circuit of said (n-1)-th processor with an n-th channel acquisition prohibition signal indicating that acquisition of the system input/output channel by said (n-1)-th processor is prohibited when the n-th monitored result signal indicates that a failure occurred in said (n-1)-th processor, and

said n-th input/output channel acquisition control circuit receiving an (n+2)-th monitored result signal, the n-th input/output channel acquisition request signal, and an (n+1)-th channel acquisition prohibition signal,

said n-th CPU, an (n+1)-th CPU of said (n+1)-th processor, and said n-th input/output channel acquisition control circuit determining whether or not the system input/output channel can be acquired on the basis of the (n+2)-th monitored result signal and the (n+1)-th input/output channel acquisition prohibition signal, said n-th input/output channel acquisition control circuit supplying, in response to the n-th input/output channel acquisition request signal, said input/output control device with an n-th input/output channel acquisition signal on the basis of the (n+2)-th monitored result signal and of the (n+1)-th channel acquisition prohibition signal.

7. A computer system comprising:

first and second processors which are provided with first and second input/output channels, respectively; and

an input/output control device coupled to the first and the second input/output channels and to a system input/output channel for a controlled system, said input/output control device configured to connect the system input/output channel to one of the first and the second input/output channels,

said first processor comprising a first central processing unit CPU) connected to the first input/output channel, said first CPU managing the first processor, a first failure detecting circuit connected to said second processor for monitoring an operation state in said second processor, and a first input/output channel acquisition control circuit connected to said first CPU, said first failure detecting circuit, said input/output control device, and said second processor for directing a control operation of said input/output control device,

said second processor comprising a second CPU connected to the second input/output channel, said second CPU managing the second processor, a second failure detecting circuit connected to said first processor for monitoring an operation state in said first processor, and a second input/output channel acquisition control circuit connected to said second CPU, said second failure detecting circuit, said input/output control device, and said first processor for directing said control operation of said input/output control device, wherein

said first CPU periodically produces a first periodic signal indicative of the operation state of the first CPU,

said second CPU periodically producing a second periodic signal indicative of the operation state of the second CPU,

said first failure detecting circuit monitors the operation state in the second processor by receiving the second periodic signal to deliver a first monitored result signal to said first CPU and said first input/output channel acquisition control circuit,

said second failure detecting circuit monitors the operation state in the first processor by receiving the first periodic signal to deliver a second monitored result signal to said second CPU and said second input/output channel acquisition control circuit,

said first CPU supplies said first input/output channel acquisition control circuit with a first input/output channel acquisition request signal when said first CPU requires acquisition of the system input/output channel,

said first CPU supplies said second input/output channel acquisition control circuit with a first channel acquisition prohibition signal indicating that acquisition of the system input/output channel by said second processor is prohibited when said first monitored result signal indicates that a failure occurred in said second processor,

said second CPU supplies said second input/output channel acquisition control circuit with a second input/output channel acquisition request signal when said second CPU requires acquisition for the system input/output channel,

said second CPU supplies said first input/output channel acquisition control circuit with a second channel acquisition prohibition signal indicating that acquisition of the system input/output channel by said first processor is prohibited when the second monitored result signal indicates that a failure occurred in said first processor,

said first input/output channel acquisition control circuit receiving the first monitored result signal, the first input/output channel acquisition request signal, and the second channel acquisition prohibition signal from said first failure detecting circuit,

said first CPU,said second CPU, and said first input/output channel acquisition control circuit determining whether or not the system input/output channel may be acquired on the basis of the first monitored result signal and the second channel acquisition prohibition signal, said first input/output channel acquisition control circuit supplying, in response to the first input/output channel acquisition request signal, a first input/output channel acquisition signal to said input/output control device on the basis of the first monitored result signal and the second channel acquisition prohibition signal, and

said second input/output channel acquisition control circuit receiving the second monitored result signal, the second input/output channel acquisition request signal, and the first channel acquisition prohibition signal,

said second CPU, said first CPU, and said second input/output channel acquisition control circuit determining whether or not the system input/output channel may be acquired on the basis of the second monitored result signal and the first channel acquisition prohibition signal, said second input/output channel acquisition control circuit supplying, in response to the second input/output channel acquisition request signal, a second input/output channel acquisition signal to said input/output control device on the basis of the second monitored result signal and the first channel acquisition prohibition signal.

8. A computer system comprising:

first through N-th processors which are provided with first through N-th internal buses connected to first through N-th bus drivers, respectively, where N represents a positive integer which is not less than two, where n represents each of integers 1 through N, and where;

When n is equal to N, an n+1)-th processor corresponds to the first processor and an (n+2)-th processor corresponds to a second processor,

when n is equal to N-1, the (n+2)-th processor corresponds to the first processor,

when n is equal to 1, an (n-1)-th processor corresponds to the N-th processor and an (n-2)-th processor corresponds to an (N-1)-th processor, and

when n is equal to 2, the (n-2)-th processor corresponds to the N-th processor; and

an outer bus coupled to the first through the N-th bus drivers and to a system input/output channel for a controlled system.

an n-th processor comprising;

an n-th central processing unit (CPU) connected to an n-th internal bus, the (n-1)-th processor, and the (n+1)-th processor, said n-th CPU managing the n-th processor,

an n-th failure detecting circuit connected to said (n-1)-th processor and said (n-2)-th processor for monitoring an operation state in said (n-1)-th processor, and

an n-th bus driver control circuit connected to said n-th CPU, an n-th bus driver, said (n+1)-th processor, and said (n+2)-th processor for directing a control operation of the n-th bus driver, wherein

said n-th CPU periodically supplies said (n+1)-th processor with an n-th periodic signal indicative of an operation state of the n-th CPU,

said n-th failure detecting circuit monitors the operation state of said (n-1)-th processor by receiving an (n-1)-th periodic signal from said (n-1)-th processor, said n-th failure detecting circuit delivering an n-th monitored result signal to said n-th CPU and said (n-2)-th processor,

said n-th CPU supplies said n-th bus driver control circuit with an n-th bus driver control request signal when said n-th CPU requires use of said outer bus,

said n-th CPU supplies an n-th bus output prohibition signal to an (n-1)-th bus driver control circuit of said (n-1)-th processor, said n-th bus output prohibition signal indicating that bus output by said (n-1)-th processor is prohibited when the n-th monitored result signal indicates that a failure occurred in said (n-1)-th processor, and

said n-th bus driver control circuit receives an (n+2)-th monitored result signal, the n-th bus driver control request signal, and an (n+1)-th bus output prohibition signal,

said n-th CPU, an (n+1)-th CPU of said (n+1)-th processor, respectively, and said n-th bus driver control circuit determining whether or not the outer bus may be used on the basis of the (n+2)-th monitored result signal and the (n+1)-th bus output prohibition signal, said n-th bus driver control circuit supplying, in response to the n-th bus driver control request signal, an n-th bus driver control signal to said n-th bus driver on the basis of the (n+2)-th monitored result signal and of the (n+1)-th bus output prohibition signal.

9. A computer system comprising:

a plurality of processors, including a particular processor and first through fourth processors, each of said processors having an input/output information transmission path connected to a controlled system input/output information transmission path via an input/output information transmission path control device;

each of said processors comprising;

failure detecting means for monitoring an operation state in another of the processors,

CPU, and

input/output information transmission path acquisition control means for directing a control operation of said input/output information transmission path control device;

said particular processor monitoring said first processor, said first processor monitoring said second processor, said third processor monitoring said particular processor, and said fourth processor monitoring said third processor, wherein

said failure detecting means in the particular processor monitors an operation state in the first processor to deliver a particular monitored result to a CPU means in the particular processor and to an input/output information transmission path acquisition control means in the second processor,

said CPU means in the particular processor supplies an operation state in the particular processor to a failure detecting means in the third processor,

said CPU means in the particular processor supplies an acquisition request for the controlled system input/output information transmission path to a input/output information transmission path acquisition control means in the particular processor when said CPU means in the particular processor requires acquisition of the controlled system input/output information transmission path,

said CPU means in the particular processor supplies, in response to the operation state in said first processor received from said failure detecting means in the particular processor, a path acquisition allowable signal to an input/output information transmission path acquisition control means in said first processor, said path acquisition allowable signal indicating whether or not the first processor may acquire the controlled system input/output information transmission path,

said input/output information transmission path acquisition control means in said particular processor receiving an operation state signal indicative of an operation state in said third processor from a failure detecting means in the fourth processor,

said input/output information transmission path acquisition control means in said particular processor providing a determination of whether or not the controlled system input/output information transmission path may be acquired on the basis of the operation state signal and a path acquisition allowable signal from said third processor,

said input/output information transmission path acquisition control means in said particular processor directing, in response to the acquisition request for the input/output information transmission path supplied from said CPU means in the particular processor, said input/output information transmission path control device to control the acquisition of the controlled system input/output information transmission path on the basis of said determination.

10. A computer system as claimed in claim 9, wherein said plurality of processors are assigned with processor numbers of 1 to N, respectively, where the particular processor corresponds to an I-th processor, where I represents each of 1 through;

said first, said second, said third, and said fourth processors correspond to an (I-1)-th processor, an (I-2)-th processor, an (I+1)-th processor, and an (I+2)-th processor, respectively; and

where

when I is equal to N, the (I+1)-th processor corresponds to the 1-th processor and the (I+2)-th processor corresponds to a 2-th processor,

when I is equal to N-1, the (I+2)-th processor corresponds to the 1-th processor,

when I is equal to 1, an (I-1)-th processor corresponds to the N-th processor and an (I-2)-th processor corresponds to an (N-1)-th processor, and

when I is equal to 2, the (I-2)-th processor corresponds to the N-th processor.

11. A computer system comprising:

a plurality of processors, including a particular processor and a first through fourth processor, each of said processors having an input/output information transmission path connected to a controlled system input/output information transmission path Via an input/output information transmission path control device;

each of said processors comprising;

failure detecting means for monitoring an operation state in another of the processors,

CPU means, and

input/output information transmission path acquisition control means for directing a control operation of said input/output information transmission path control device;

said particular processor monitoring said first processor, said first processor monitoring said second processor, said third processor monitoring said particular processor, and said fourth processor monitoring said third processor;

said failure detecting means in the particular processor monitoring an operation state in the first processor to deliver monitored result to a CPU means in the particular processor and to a input/output information transmission path acquisition control means in the second processor;

said CPU means supplying an operation state in the particular processor to a failure detecting means in the third processor,

said CPU means supplying an acquisition request for the input/output information transmission path to an input/output information transmission path acquisition control means in the particular processor when said CPU means in the particular processor requires acquisition of the controlled system input/output information transmission path,

said CPU means in the particular processor supplying a path acquisition inhibition signal to said input/output information transmission path acquisition control means in said first processor, said path acquisition inhibition signal being indicative of inhibition of the acquisition for the controlled system input/output information transmission path by said first processor when processor operation state signal supplied from said failure detecting means in the particular processor indicates that there is failure in the operation state in said first processor;

said input/output information transmission path acquisition control means in the particular processor receiving a third processor operation state signal indicative of the operation state in said third processor from a failure detecting means in the fourth processor, when the third processor operation state signal indicates that there is failure in said third processor, said input/output information transmission path acquisition control means in the particular processor directing, on the basis of the acquisition request for the input/output information transmission path supplied from said CPU means in the particular processor, said input/output information transmission path control device to control the acquisition of the input/output information transmission path in defiance of a path acquisition allowable signal which is transmitted from said third processor and which indicates whether or not the particular processor may acquire the controlled system input/output information transmission path, when the third processor operation state signal indicates that there is no failure in said third processor, said input/output information transmission path acquisition control means directing said input/output information transmission path acquisition control device to control the acquisition of the controlled system input/output information transmission path by processing the acquisition request for the input/output information transmission path supplied from said CPU means in the particular processor in accordance with the path acquisition allowable signal which is transmitted from said third processor and which indicates whether or not the particular processor may acquire the input/output information transmission path.

12. A computer system as claimed in claim 11, wherein said failure detecting means in the particular processor produces the first processor operation state signal having a logic one value when said first processor has the operation state of normal, said failure detecting means in the particular processor producing the first processor operation state signal having a logic zero value when a failure occurs in said first processor;

said CPU means in the particular processor supplying said input/output information transmission path acquisition control means of said first processor with the path acquisition inhibition signal having a logic one value indicative of inhibition of the acquisition for the input/output information transmission path by said first processor when the first processor operation state signal supplied from said failure detecting means in the particular processor indicates that there is failure in the operation state in said first processor;

said input/output information transmission path acquisition control means in the particular processor comprising an AND circuit and an OR circuit;

said AND circuit having a first input terminal supplied with the third processor operation state signal produced by said failure detecting means of said fourth processor;

said AND circuit having a second input terminal supplied with the path acquisition allowable signal transmitted from said third processor;

said OR circuit having a first input terminal supplied with the acquisition request for the input/output information transmission path from said CPU means in the particular processor; and

said OR circuit having a second input terminal supplied with an output of said AND circuit, thereby directing said input/output information transmission path control device to operate control for the acquisition of the input/output information transmission path on the basis of an output of said OR circuit.

13. A computer system as claimed in claim 11, wherein said controlled system input/output information transmission path is composed of a bus, and said input/output information transmission path control device comprises a bus driver in each processor.

14. A computer system as claimed in claim 11, wherein said controlled system input/output information transmission path is composed of a channel, and said input/output information transmission path control device comprises a channel connection switching control device which is provided for said processors in common.