Dynamic processor performance and power management in a computer system

• US 5,630,148 A
• Filed: 02/28/1996
• Issued: 05/13/1997
• Est. Priority Date: 06/17/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Norris, David
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Travis, John
• Application Number:
  US08/613,778
• Time in Patent Office: 440 Days
• Field of Search: 395/750, 395/159, 364/707
• US Class Current: 713/322
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 11/34 Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
• CPC Class Codes: G06F 11/3419 by assessing time
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system is disclosed comprising a clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register, wherein the processor executes a performance manager program that writes the clock speed register according to a performance state selected by an application program. The application program selects the performance state to maximize performance during processor intensive functions and to maximize power conservation during interactive functions.

Claims

1. A computer system, comprising:

clock generator circuit having a clock speed register and circuitry for generating a processor clock signal at a frequency determined by the clock speed register;

storage means for storing processor instructions;

processor coupled to the clock generator circuit to receive the processor clock signal such that the processor clock signal synchronizes the processor, the processor coupled to the storage means to fetch and execute a performance manager program that writes the clock speed register according to a performance state selected by an application program to be executed by the processor, the performance state having been selected from a performance state table maintained by the performance manager program.

2. The computer system of claim 1, wherein the processor writes the clock speed register with a value specified in a performance state table maintained by the performance manager program.

3. The computer system of claim 2, wherein the performance state table stores a set of clock frequencies that correspond to a set of performance states for the processor.

4. The computer system of claim 3, further comprising a performance control panel program for execution on the computer system that enables a user to select the clock frequencies for the performance states of the processor.

5. The computer system of claim 3, wherein the performance manager program writes the clock speed register with one of the clock frequencies corresponding to a high performance state specified by a system call from the application program as the application program begins a processor intensive function.

6. The computer system of claim 3, wherein the performance manager program writes the clock speed register with one of the clock frequencies corresponding to a low performance state specified by a system call from the application program as the application program ends a processor intensive function.

7. The computer system of claim 3, wherein the performance manager program writes the clock speed register by invoking a clock generator driver program of a set of basic input/output software for the computer system.

8. The computer system of claim 1 wherein the storage means comprises non-volatile memory and a memory sub-system.

9. A method for managing performance and power consumption of a computer system, comprising the steps of:

generating a processor clock signal at a frequency determined by a clock speed register;

synchronizing a processor of the computer system with the processor clock signal;

writing the clock speed register with a value specified in a performance state table maintained by a performance manager program executed by the processor, the value corresponding to a performance state selected by an application program being executed by the processor.

10. The method of claim 9, wherein the performance state table stores a set of clock frequencies that correspond to a set of performance states for the processor.

11. The method of claim 10, further comprising the step of selecting the clock frequencies for the performance states of the processor using a performance control panel program executed on the computer system.

12. The method of claim 11, wherein the step of writing the clock speed register according to a performance state selected by an application program comprises the step of writing the clock speed register with one of the clock frequencies corresponding to a high performance state specified by a system call from the application program as the application program begins a processor intensive function.

13. The method of claim 11, wherein the step of writing the clock speed register according to a performance state selected by an application program comprises the step of writing the clock speed register with one of the clock frequencies corresponding to a low performance state specified by a system call from the application program as the application program ends a processor intensive function.

14. The method of claim 11, wherein the step of writing the clock speed register according to a performance state selected by an application program comprises the step of invoking a clock generator driver program of a set of basic input/output software for the computer system.

15. The method of claim 11, further comprising the step of generating an accelerate button on a display device, such that a user selects the accelerate button to cause the performance manager program to write the clock speed register with one of the clock frequencies corresponding to a high performance state of the processor.