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Array processor dotted communication network based on H-DOTs

  • US 5,630,162 A
  • Filed: 04/27/1995
  • Issued: 05/13/1997
  • Est. Priority Date: 11/13/1990
  • Status: Expired due to Term
First Claim
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1. A parallel SIMD or MIMD array processor communication network, comprising:

  • a plurality of processing elements interconnected in an array topology configuration, each of the processing elements having at least two ports for communication with other processing elements;

    a plurality of physical links, each physical link providing an interconnection among four processing elements of said plurality of processing elements, said physical link having four ports respectively coupled to one of the ports for each of the four processing elements, and having a common low impedance connection among the four ports of the physical link such that any said one of the ports for each of the four processing elements is coupled by a low impedance path through said physical link to another one of the ports of the four processing elements over the physical link, and wherein said physical link is independent of providing a common, physical bus interconnection between a first, second, and third processing element for any identically specified direction and dimension relationship, according to the array topology, between the first and the second processing element and between the second and the third processing element; and

    a communications control mechanism in each of the four processing elements operative in transferring a message from one of the four processing elements to another one of the four processing elements over the physical link.

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