Array processor dotted communication network based on H-DOTs

• US 5,630,162 A
• Filed: 04/27/1995
• Issued: 05/13/1997
• Est. Priority Date: 11/13/1990
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kogge, Peter M., Wilkinson, Paul A.
• Primary Examiner(s): Geckil, Mehmet B.
• Application Number:
  US08/430,708
• Time in Patent Office: 747 Days
• Field of Search: 395/200, 395/800, 395/725, 395/200.1, 395/200.02, 364/734-736, 364/131, 364/133, 370/94.1-94.3, 370/60, 370/86
• US Class Current: 712/20
• CPC Class Codes: G06F 15/17337 Direct connection machines, e.g. completely connected computers, point to point communication networks coupling between buses G06F13/4004
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]

Abstract

A parallel processor array of the SIMD or MIMD type requires a highly organized communication network for communication between processing elements (PEs). For a communication network a dotted network structure is created which reduces the magnitude of the the networking implementation using a link with two vertical paths and two horizontal paths for a single link, denominated H-DOT. A significant result of the H-DOT network configuration is that it applies to several topologies, and furthermore, the array of processors can generally be extended in size and in additional dimensions while retaining the basic two port array processing element. Both synchronous and routed control can be included. Routing algorithm routines are discussed. The network configuration can be used in massively parallel processors or other smaller array processors which can implement SIMD and MIMD processes.

Claims

1. A parallel SIMD or MIMD array processor communication network, comprising:

a plurality of processing elements interconnected in an array topology configuration, each of the processing elements having at least two ports for communication with other processing elements;

a plurality of physical links, each physical link providing an interconnection among four processing elements of said plurality of processing elements, said physical link having four ports respectively coupled to one of the ports for each of the four processing elements, and having a common low impedance connection among the four ports of the physical link such that any said one of the ports for each of the four processing elements is coupled by a low impedance path through said physical link to another one of the ports of the four processing elements over the physical link, and wherein said physical link is independent of providing a common, physical bus interconnection between a first, second, and third processing element for any identically specified direction and dimension relationship, according to the array topology, between the first and the second processing element and between the second and the third processing element; and

a communications control mechanism in each of the four processing elements operative in transferring a message from one of the four processing elements to another one of the four processing elements over the physical link.

2. An array processor communication network according to claim 1 wherein the array topology configuration is represented by a plurality of dimensions, and an address of each processing element is represented as a series of digits with each digit representing a location of the processing element in one of the plurality of dimensions, and wherein the physical link connects together processing elements that have addresses differing in only 1 address digit.

3. An array processor communication network according to claim 1 wherein the array topology configuration is a two dimensional mesh topology.

4. A two dimensional array processor communication network according to claim 3 wherein the plurality of processing elements are interconnected to provide for a first processing element to interconnect to a nearest neighbor processing element by a common physical link that provides two logical vertical paths and two logical horizontal paths, one of the two logical vertical paths being between the first processing element and a second processing element, the other of the two logical vertical paths being between a third processing element and a fourth processing element, one of the two logical horizontal paths being between the first processing element and the third processing element, the other of the logical horizontal paths being between the second processing element and the fourth processing element, thereby forming an H connection.

5. An array processor communication network according to claim 1 wherein the array topology configuration is a three dimensional mesh topology.

6. An array processor communication network according to claim 1 wherein the array topology configuration is a mesh topology of more than 3 dimensions.

7. An array processor communication network according to claim 1 wherein the array topology configuration is a binary n-cube topology.

8. An array processor communication network according to claim 1 wherein the array topology configuration is a sparse Base 4 n-cube topology.

9. An array processor communication network according to claim 1 wherein the way topology configuration is a sparse n-cube having a base greater than two.

10. An array processor communication network according to claim 1 wherein the communication control mechanism is operative in transferring messages of the synchronous type or of the routed type.

11. An array processor communication network according to claim 10, wherein said communications control mechanism includes a routing algorithm executed by the processing elements for transferring messages of the routed type, wherein said routing algorithm comprises an ACCEPT routine, and a KEEP routine.

12. An array processor communication network according to claim 11 wherein each processing element has a two ports, and wherein the routing KEEP routine of a given processing element having a given address is implemented by keeping a message containing a destination address received at one of the two ports if the destination address matches the given address, else passing the message out the other of the two ports.

13. An array processor communication network according to claim 11 wherein the routing ACCEPT routine of a processing element determines when the processing element should access a message on either of two ports of the processing element.

14. An array processor communication network according to claim 13 where the processing element having a first address has ports to a multidimensional quadrant, and the routing ACCEPT routine accepts a message having a given address if the given address is either the first address of the processing element, or else an address of any processing element located in the multidimensional quadrant.

15. An array processor communication network according to claim 1 where the array can be extended in area or in dimensions by adding to the existing interconnection network, or by adding additional networks.

16. The array processor communication network according to claim 1, further comprising an array controller coupled to each of the processing elements, and wherein said communication control mechanism is operative in transferring messages of the synchronous type in response to a signal received from the array controller.

17. The array processor communication network according to claim 1, wherein said communication control mechanism is operative in transferring messages of the routed type according to a routing control algorithm executed by the processing elements.

18. A parallel SIMD or MIMD array processor communication network, comprising:

a plurality of processing elements interconnected in an array topology configuration, each of the processing elements having at least two ports for communication with other processing elements;

a physical link providing an interconnection among four processing elements of said plurality of processing elements, said physical link having four ports respectively coupled to one of the ports for each of the four processing elements, and having a common low impedance connection among the four ports of the physical link such that any said one of the ports for each of the four processing elements is coupled by a low impedance path through said physical link to another one of the ports of the four processing elements over the physical link; and

a communications control mechanism in each of the four processing elements operative in transferring a message of the synchronous type or of the routed type from one of the four processing elements to another one of the four processing elements over the physical link;

wherein said communications control mechanism includes a routing algorithm executed by the processing elements for transferring messages of the routed type, wherein said routing algorithm comprises an ACCEPT routine, and a KEEP routine, wherein the routing ACCEPT routine of a processing element determines when the processing element should access a message on either of two ports of the processing element; and

wherein one of said processing elements having a first address has ports to a multidimensional quadrant, and the routing ACCEPT routine accepts a message having a given address if the given address is either the first address of the processing element, or else an address of any processing element located in the multidimensional quadrant.