Translating from a PIO protocol to DMA protocol with a peripheral interface circuit

• US 5,630,171 A
• Filed: 06/20/1996
• Issued: 05/13/1997
• Est. Priority Date: 10/20/1992
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Cline, Leslie E., Curt, Kenneth C., Chejlava, Edward J. Jr.
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US08/667,914
• Time in Patent Office: 327 Days
• Field of Search: 395/821-883, 395/200, 395/500
• US Class Current: 710/23
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.

Claims

1. A method of transferring information from a CPU to a disk drive, comprising the steps of:

transferring information from the CPU to an interface circuit over a computer bus using a PIO protocol, the CPU being incapable of transferring information to the interface circuit over the computer bus using DMA; and

transferring the information from the interface circuit to the disk drive over a peripheral bus using DMA, wherein the DMA is initiated at least in part by the interface circuit receiving a DMA request signal on the peripheral bus, the DMA request signal not being used to arbitrate for the peripheral bus, the interface circuit outputting a DMA acknowledge signal onto the peripheral bus which causes the information to be transferred into a predetermined location in the disk drive.

2. The method of claim 1, wherein the predetermined location is an ATA drive data register of the disk drive.

3. The method of claim 1, further comprising the steps of:

storing in the interface circuit characteristics of the disk drive; and

providing control signals to the interface circuit based on the stored characteristics to transfer information between the interface circuit and the disk drive, wherein the stored characteristics from the storing step control the timing of the control signals.

4. The method of claim 1, wherein the CPU can selectably control the interface circuit and the disk drive to transfer information between the interface circuit and the disk drive by DMA or by another type of transfer.

5. The method of claim 1, wherein a peripheral device other than the disk drive is coupled to the peripheral bus, the method further comprising the steps of:

transferring second information from the computer bus to the interface circuit using a PIO protocol; and

transferring the second information from the interface circuit to the peripheral device using a PIO protocol.

6. A method of transferring information from a host device to a peripheral device, comprising the steps of:

transferring information from the host device to an interface circuit over a computer bus using a PIO protocol, the host device being incapable of transferring information to the interface circuit over the computer bus using DMA; and

transferring the information from the interface circuit to the peripheral device over a peripheral bus using DMA, wherein the DMA is initiated at least in part by the interface circuit receiving a DMA request signal on the computer bus, the DMA request signal not being used to arbitrate for the peripheral bus, the interface circuit outputting a DMA acknowledge signal onto the peripheral bus which causes the information to be transferred into a predetermined location in the peripheral device.

7. A method of transferring information from a disk drive to a CPU via an interface circuit, comprising the steps of:

transferring information from the disk drive to the interface circuit over a peripheral bus using DMA, wherein the DMA is initiated at least in part by the interface circuit receiving a DMA request signal on the peripheral bus, the DMA request signal not being used to arbitrate for the peripheral bus, the interface circuit outputting a DMA acknowledge signal onto the peripheral bus which causes the information to be transferred out of the disk drive; and

transferring the information from the interface circuit to the CPU over a computer bus using a PIO protocol, the CPU being incapable of receiving information from the interface circuit over the computer bus using DMA.