Apparatus and methods of closed loop calibration of infrared focal plane arrays

• US 5,631,466 A
• Filed: 06/16/1995
• Issued: 05/20/1997
• Est. Priority Date: 06/16/1995
• Status: Expired due to Term

• Current Assignee: OL Security LLC (Intellectual Ventures LLC)
• Original Assignee: Hughes Electronics Corporation (AT&T, Inc.)
• Inventors: Botti, Dominic J., Hutchens, Vernon F.
• Primary Examiner(s): NOLAND, THOMAS
• Application Number:
  US08/491,134
• Time in Patent Office: 704 Days
• Field of Search: 73/1 R, 250/252.1 R, 250/341.5, 250/332, 250/252.1 A, 364/571.04, 364/571.05, 364/571.06, 364/571.07, 364/571.08
• US Class Current: 250/332
• CPC Class Codes: H04N 17/002 for television cameras
• CPC Class Codes: H04N 25/20 for transforming only infrared radiation into image signals
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

A calibration circuit (40) for infrared detectors including a first circuit (72) for storing a value representing the level of a first output of each detector in response to the illumination of the detector by a first target. A second circuit (74) stores a value representing the responsivity of each detector in response to the illumination of the detector by the first target. A third circuit (48), responsive to the first circuit (72), adjusts the level of the output of each detector in response to a second target and provides a level adjusted signal in response thereto. A fourth circuit (52), responsive to the second circuit (74), adjusts the responsivity of each detector in response to the second target and provides a responsivity adjusted signal in response thereto. A fifth circuit (58, 60, 62) feeds the output of the third circuit (48) back to the first circuit. (72). Finally, a sixth circuit (58, 60, 62) feeds the output of the fourth circuit (52) back to the second circuit (74). The invention performs level and responsivity equalization processing on the analog output of an Infrared Focal Plane Array (IRFPA), when in imaging mode and calculates the digital data for performing the equalization, when in calibration mode. Novel features of the invention include the use of close loop feedback in the calibration mode, the following ways: 1) The processed output is used to incrementally improve the digital level equalization (LE) or responsivity equalization (RE) value for each pixel. 2) The convergence target of the closed loop algorithm is programmable to any analog to digital converter (ADC) output code. 3) Data analysis of entire image frames of the processed ADC output is used set the value of the convergence target at each step of calibration (a secondary term of feedback). 4) Saturation logic guarantees stability of the loop and facilitates the detection of dead pixels.

Claims

1. A calibration system for a staring imaging sensor having an array of detectors, the system comprising:

first means for storing a value representing the level of a first output of each detector in response to the illumination of said detector by a first target;

second means for storing a value representing the responsivity of each detector in response to said illumination of said detector by said first target;

third means responsive to the first means for adjusting the level of the output of each detector in response to a second target and providing a level adjusted signal in response thereto;

fourth means responsive to said second means for adjusting the responsivity of each detector in response to said second target and providing a responsivity adjusted signal in response thereto;

fifth means for feeding the output of said third means back to said first means; and

sixth means for feeding the output of said fourth means back to said second means.

2. The invention of claim 1 wherein said fifth and said sixth means include a digital subtracter for adjusting the outputs of said third means and said fourth means by a convergence target.

3. The invention of claim 2 including means for rescaling the output of said digital subtracter by filter constant.

4. The invention of claim 3 including data analysis means for analyzing the output of said third means and said fourth means to provide a histogram of data.

5. The invention of claim 4 including processing control means for providing said convergence target and said filter constant in response to said histogram.

6. The invention of claim 5 wherein said processing control means includes means for selectively providing a level equalization constant to said first means and a responsivity equalization constant to said second means.

7. The invention of claim 5 wherein said processing control means includes means for selectively providing a level equalization constant and a responsivity equalization constant to the output of said rescaling logic means.

8. The invention of claim 1 further including saturation logic for identifying dead detectors.

9. The invention of claim 1 including data analysis means for analyzing the output of said third means and said fourth means to provide a histogram of data.

10. The invention of claim 9 wherein said data analysis means includes means for using pixels in a selected region of the image to provide a histogram.

11. The invention of claim 1 including means for using pixels in a selected region of the image to provide a range count.

12. The invention of claim 1 including means for providing a count of pixels ADC codes within a selected range.