MOS-technology power device chip and package assembly

• US 5,631,476 A
• Filed: 08/01/1995
• Issued: 05/20/1997
• Est. Priority Date: 08/02/1994
• Status: Expired due to Term

• Current Assignee: Consorzio Per Il Sistema Informativo Csi Piemonte, SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: Consorzio Per Il Sistema Informativo Csi Piemonte, SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Inventors: Frisina, Ferruccio, Ferla, Giuseppe
• Primary Examiner(s): BROWN, PETER T
• Application Number:
  US08/509,956
• Time in Patent Office: 658 Days
• Field of Search: 257/177, 257/181, 257/584, 257/587, 257/666, 257/675, 257/691, 257/693, 257/696, 257/724, 257/728
• US Class Current: 257/177
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

In a MOS-technology power device chip and package assembly, the MOS-technology power device chip comprises a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and including a first doped region of a first conductivity type formed in the semiconductor layer, and a second doped region of a second conductivity type formed inside the first doped region; the package comprises a plurality of pins for the external electrical and mechanical connection; the plurality of elementary functional units is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities; each of the metal plates are connected, through a respective bonding wire, to a respective pin of the package.

Claims

1. MOS-technology power device chip and package assembly, MOS-technology power device chip comprising a semiconductor material layer in which a plurality of elementary functional units is integrated, each elementary functional unit contributing a respective fraction to an overall current and comprising a first doped region of a first conductivity type formed in said semiconductor layer, and a second doped region of a second conductivity type formed inside said first doped region, the package comprising a plurality of pins for the external electrical and mechanical connection, wherein said plurality of elementary functional units is composed of sub-pluralities of elementary functional units, the second doped regions of all the elementary functional units of each sub-plurality being contacted by a same respective metal plate electrically insulated from the metal plates contacting the second doped regions of all the elementary functional units of the other sub-pluralities, each of said metal plates being connected, through a respective bonding wire, to a respective pin of the package.

2. MOS-technology power device chip and package assembly according to claim 1, wherein said sub-pluralities of elementary functional units are separated by regions of said semiconductor layer in which no elementary functional units are integrated.

3. MOS-technology power device chip and package assembly according to claim 2, wherein said semiconductor material layer is selectively covered by a conductive insulated gate layer partially extending over said first doped regions, said insulated gate layer being contacted by gate metal mesh surrounding said source metal plates and connected to at least one gate metal pad which is in tarn connected, by means of a respective bonding wire, to a respective pin of the package.

4. MOS-technology power device chip and package assembly according to claim 3, wherein said gate metal mesh comprises gate metal fingers intercalated to said metal plates, and a gate metal lane surrounding the periphery of the power device chip.

5. MOS-technology power device chip and package assembly according to claim 1, wherein said semiconductor material layer comprises a lightl of the second conductivity type superimposed over a heavily doped semiconductor substrate.

6. MOS-technology power device chip and package assembly according to claim 5, wherein said semiconductor substrate is of the second conductivity type, to form a power MOSFET.

7. MOS-technology power device chip and package assembly according to claim 5, wherein said semiconductor substrate is of the first conductivity type, to form an 1GBT.

8. MOS-technology power device chip and package assembly according to claim 1, wherein said first conductivity type is P type, and said second conductivity type is N type.

9. MOS-technology power device chip and package assembly according to claim 1, wherein said first conductivity type is N type, and said second conductivity type is P type.

10. MOS-technology power device chip and package assembly according to claim 1, wherein said package is a multipin Dual-In-Line Surface Mount Technology (SMT) power package.

11. MOS-technology power device chip and package assembly according to claim 1, wherein said bonding wires have a same length.