Standard cell having a capacitor and a power supply capacitor for reducing noise and method of formation
First Claim
1. An integrated circuit standard cell comprising:
- a substrate;
a first doped substrate region within the substrate and biased to a ground voltage potential via a first metal region, the first doped substrate region having a doped portion of a first conductivity type;
a second doped substrate region within the substrate, laterally separated from the first doped substrate region, and being biased to a power supply voltage potential via a second metal region, the second doped substrate region having a doped portion of a second conductivity type which is different from the first conductivity type;
a gate oxide layer formed overlying the substrate; and
a first conductive region formed overlying the first doped substrate region and separated from the first doped substrate region by the gate oxide layer, the first conducive region being biased to the power supply voltage potential which creates an inversion region in the doped portion of the first conductivity type; and
a second conductive region formed overlying the second doped substrate region and separated from the second doped substrate region by the gate oxide layer, the second conductive region being biased to the ground voltage potential which creates an inversion region in the doped portion of the second conductivity type.
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Accused Products
Abstract
An integrated circuit (10), which is designed using standard cells (20, 22, 24, 26, 28, 30, 32, 34, 35, 36, 37, 28, 40, 42, 44, 46, 48, 50, 52), usually has one or more empty spaces (54) wherein no circuitry is formed. These empty spaces may be used to form capacitor standard cells which have capacitors (see FIGS. 3 and 4) to both ground and power supply lines within the integrated circuit. These capacitors are used to reduce noise in the power and supply lines in a manner more useful/efficient than known methods. The capacitor standard cell taught herein is more useful/efficient due to the fact that the capacitance provided by these standard cells is distributed over the entire integrated circuit in small portions (i.e., standard cells are placed all over the integrated circuit (10)), and is placed close to the logic which is switching. It is the switching logic which is the root of a large portion of internal integrated circuit noise.
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Citations
18 Claims
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1. An integrated circuit standard cell comprising:
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a substrate; a first doped substrate region within the substrate and biased to a ground voltage potential via a first metal region, the first doped substrate region having a doped portion of a first conductivity type; a second doped substrate region within the substrate, laterally separated from the first doped substrate region, and being biased to a power supply voltage potential via a second metal region, the second doped substrate region having a doped portion of a second conductivity type which is different from the first conductivity type; a gate oxide layer formed overlying the substrate; and a first conductive region formed overlying the first doped substrate region and separated from the first doped substrate region by the gate oxide layer, the first conducive region being biased to the power supply voltage potential which creates an inversion region in the doped portion of the first conductivity type; and a second conductive region formed overlying the second doped substrate region and separated from the second doped substrate region by the gate oxide layer, the second conductive region being biased to the ground voltage potential which creates an inversion region in the doped portion of the second conductivity type. - View Dependent Claims (2, 3, 4, 15, 16)
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5. A semiconductor device comprising:
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a substrate having a surface; a first doped region formed within the substrate, the first doped region being a P doped region which is used to support formation of N type source and drain regions within the P doped region, the P doped region forming an N-channel region a second doped region formed within the substrate, the second doped region being an N doped region which is used to support formation of P type source and drain regions within the N doped region, the N doped region forming a P-channel region; a dielectric layer formed overlying the surface of the substrate; a first conductive region formed overlying the dielectric layer and overlying the N-channel region; a second conductive region formed overlying the dielectric layer, laterally separated from the first conductive region, and overlying the P-channel region; a first metal conductor for providing a power supply potential, the first metal conductor being coupled to the first conductive region to form a capacitor between the first conductive region and the first doped region; and a second metal conductor for supplying a ground potential, the second metal conductor being coupled to the second conductive region to form a capacitor between the second conductive region and the second doped region. - View Dependent Claims (6, 7, 8, 17)
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9. A standard cell circuit comprising:
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a P channel transistor having a drain electrode electrically coupled to a source electrode, a gate electrode overlying a channel region which is inverted to form an inversion region within a substrate, the inversion region being biased to a ground potential and the gate electrode being biased to a power supply potential; and an N channel transistor having a drain electrode electrically coupled to a source electrode, a gate electrode overlying a channel region which is inverted to form an inversion region within a substrate, the inversion region being biased to the power supply potential and the gate electrode being biased to the ground potential, the N channel transistor being laterally adjacent the P channel transistor. - View Dependent Claims (10, 11)
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12. A standard cell layout comprising:
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a substrate; a dielectric layer formed overlying the substrate; a power supply conductor overlying the dielectric layer; a ground conductor overlying the dielectric layer; a first active region defined within the substrate and being coupled to the power supply conductor through a first plurality of contact openings formed through the dielectric layer, the first active region being of a first conductivity type; a second active region defined within the substrate and being laterally adjacent the first active region, the second active region being coupled to the ground conductor through a second plurality of contact openings formed through the dielectric layer, the second active being of a second conductivity type which is different from the first conductivity type; a first conductive layer overlying the first active region, being separated form the first active region by a first gate dielectric region, and being coupled to the ground supply conductor through a third plurality of contact openings formed through the dielectric layer; and a second conductive layer overlying the second active region, being separated form the second active region by a second gate dielectric region, and being coupled to the power supply conductor through a fourth plurality of contact openings formed through the dielectric layer. - View Dependent Claims (13, 14)
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18. A semiconductor device comprising:
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a substrate having a surface; a first doped region formed within the substrate which is an N type transistor region; a second doped region formed within the substrate which is a P type transistor region; a dielectric layer formed overlying the surface of the substrate; a first conductive region formed overlying the dielectric layer and in close proximity to the first doped region; a second conductive region formed overlying the dielectric layer, laterally separated from the first conductive region, and in close proximity to the second doped region; a first metal conductor for providing a power supply potential, the first metal conductor being coupled to the first conductive region to form a capacitor between the first conductive region and the first doped region; a second metal conductor for supplying a ground potential, the second metal conductor being coupled to the second conductive region to form a capacitor between the second conductive region and the second doped region; and wherein replicas of the semiconductor device are automatically placed by a place and route tool into a plurality of unused substrate areas on the surface of an integrated circuit die, wherein the plurality of unused substrate areas are areas not occupied by other standard logic cells, whereby the plurality of unused areas are coupled for a purpose of reducing power supply and ground supply noise via on-chip capacitors.
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Specification