Two stage current mirror

• US 5,631,599 A
• Filed: 12/13/1995
• Issued: 05/20/1997
• Est. Priority Date: 10/30/1991
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Chi, Chong I., Fisher, Gregory J., Bacrania, Kantilal
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): TON, MY TRANG
• Application Number:
  US08/571,693
• Time in Patent Office: 524 Days
• Field of Search: 307/296.6, 307/296.7, 307/296.8, 307/296.1, 323/316, 323/312, 323/315, 327/538, 327/539, 327/103, 327/542, 327/543, 327/546, 327/540, 327/541
• US Class Current: 327/542
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 3/505 with field-effect devices
• CPC Class Codes: H03G 1/0082 using bipolar transistor-type devices
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 5/15 Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors distributing, switching or gating arrangements H03K17/00
• CPC Class Codes: H03M 1/162 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/161 takes precedence
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

An A-to-D converter 300 has a comparator 126 with a number of comparator cells 902. Each comparator cell 902 includes a current mirror 1700 that reduces kickback noise. Current mirror 1700 includes a bipolar current mirror 1705 and an NMOS current mirror 1709. The bipolar current mirror 1705 provides an ac ground paralleling NMOS transistor 1704 in the NMOS current mirror 1709 to reduce kickback noise.

Claims

1. A current mirror, comprising:

(a) a first stage comprising a reference current input for receiving a reference current,

a first bipolar transistor coupled to the reference current input and having an emitter current representative of the reference current;

voltage generating means for generating a voltage proportional to a current, said voltage generating means coupled to the emitter of the first bipolar transistor for generating a voltage proportional to the emitter current of the first bipolar transistor;

a second bipolar transistor coupled to the first bipolar transistor and to the output of the first stage for generating at the emitter of the second bipolar transistor a controlled voltage representative of the reference current;

(b) a second stage with a second stage input coupled to the output of the first stage, said second stage comprising one or more output field effect transistors (FETs) with their gates coupled to the controlled voltage for generating second stage output currents in the output FETs proportional to the controlled voltage of the first stage output and representative of the reference input current.

2. The current mirror of claim 1 wherein the controlled voltage corresponds to the voltage generated by the voltage generating means.

3. The current mirror of claim 1 wherein the bases of the first and second bipolar transistors are connected to each other.

4. The current mirror of claim 1 wherein the two bipolar transistors are NPN transistors and the output FETs are NMOS transistors.

5. The current mirror of claim 4 wherein the voltage generating means comprises a diode connected NMOS transistor.

6. The current mirror of claim 1 wherein the two bipolar transistors are PNP transistors and the output FETs are PMOS transistors.

7. The current mirror of claim 6 wherein the voltage generating means comprises a diode connected PMOS transistor.

8. The current mirror of claim 1 wherein the second stage further comprises current generating means coupled to the emitter of the second bipolar transistor for generating a current proportional to the emitter voltage.

9. The current mirror of claim 8 wherein the voltage generating means of the first stage and the current generating means of the second stage are identical FETs.

10. The current mirror of claim 8 wherein the current generating means comprises a diode connected NMOS transistor.

11. The current mirror of claim 10 wherein the gate and the drain of the current generating NMOS transistor are connected to the controlled voltage.

12. The current mirror of claim 8 wherein the current generating means comprises a diode connected PMOS transistor.

13. The current mirror of claim 12 wherein the gate and the drain of the current generating PMOS transistor are connected to the controlled voltage.

14. The current mirror of claim 1 wherein the first stage further comprises base compensation circuitry connected to the bases of the first and second bipolar transistors for compensating the base current of the first and second bipolar transistors.

15. The current mirror of claim 14 wherein the base compensation circuitry comprises a third bipolar transistor having its base coupled to the collector of the first transistor and its emitter coupled to the base of the second bipolar transistor.

16. The current mirror of claim 15 wherein the base compensation circuitry further comprises a fourth bipolar transistor in series with a FET for further compensating the base current in the first and second bipolar transistors.

17. The current mirror of claim 1 wherein the diode connected FET provides a first impedance path for spurious signals on the gates of the output FETS and the second bipolar transistor provides a second impedance path for such spurious gate signals, said second impedance path being substantially less than the impedance of the first impedance path.

18. The current mirror of claim 1 wherein each of the first bipolar transistor, the voltage generating means and each output FET is serially connected to a diode-connected FET.

19. A method of mirroring currents, comprising the steps of:

providing first and second stages in a current mirror, said first stage comprising first and second bipolar transistors;

providing an input reference current to the collector of the first bipolar transistor;

generating a voltage at the emitter of the first transistor representative of the input reference current;

generating a controlled output voltage at the emitter of the second bipolar transistor representative of the input reference current;

connecting gates of one or more output FETs to the controlled voltage to provide one or more output currents representative of the input reference current.

20. The method of claim 19 wherein the voltage generated at the emitter of the first bipolar transistor corresponds to the controlled voltage at the emitter of the second bipolar transistor.

21. The method of claim 19 wherein the bipolar transistors are NPN transistors and the FETs are NMOS FETs.

22. The method of claim 19 wherein the bipolar transistors are PNP transistors and the FETs are PMOS FETs.

23. The method of claim 19 further comprising the step of generating a current proportional to the second emitter voltage.