Parallel approach to chip wiring

• US 5,631,842 A
• Filed: 03/07/1995
• Issued: 05/20/1997
• Est. Priority Date: 03/07/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Habra, Rafik R., Schanzenbach, Erich C.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/400,408
• Time in Patent Office: 805 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 357/68, 357/45, 235/151.1
• US Class Current: 716/130
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

In any of the post-global physical design phases an integrated circuit chip is wired in parallel. The chip is first divided into adjacent bays with rough wiring coordinates from the global wiring phase. Next the bays are grouped into bay groups, with each bay group containing a contiguous group of non-edge bays as well as edge bays which are adjacent another bay group. Each bay group is assigned to a wiring task on a processor, so that the wiring of the bay groups is performed in parallel, using the rough coordinates from the global wiring phase. The wiring tasks are coordinated regarding edge bays in order to achieve wiring consistency between bay groups.

Claims

1. A method for wiring areas on an integrated circuit chip in parallel, comprising the steps of:

(a) dividing said chip into a plurality of rectangular bays with rough wiring coordinates;

(b) grouping said rectangular bays into a plurality of bay groups, each bay group containing a contiguous group of bays including non-edge bays and at least one edge bay adjacent another bay group;

(c) assigning a different bay group to each wiring task of a plurality of wiring tasks; and

(d) each of said wiring tasks including performing of wiring of said bays in a bay group assigned thereto according to said rough coordinates and performing said wiring in parallel with said other wiring tasks,

(1) if wiring an edge bay, before wiring begins checking whether the adjacent edge bay has been wired, is currently being wired, or has not been wired, and

(i) if said adjacent edge bay has been wired, wiring said edge bay in accordance with said adjacent edge bay wiring, or

(ii) if said adjacent edge bay is currently being wired, waiting for said adjacent edge bay to finish being wired and then wiring said edge bay in accordance with said adjacent edge bay wiring, or

(iii) if said adjacent edge bay has not been wired, wiring said edge bay, otherwise wiring said non-edge bay.

2. The method of claim 1 wherein each wiring task is controlled by a respective computer processor.

3. The method of claim 2 wherein the wiring of said edge bay in accordance with said adjacent edge bay is performed by accessing a database of detailed wiring data for said plurality of bays.

4. The method of claim 1 further comprising the steps of:

(e) assigning a next available unwired bay group to a task that has completed wiring its assigned bay group; and

(f) repeating steps (d) and (e) until all unwired bay groups have been assigned to wiring tasks.

5. The method of claim 4 further comprising the step of merging said wiring of said bay groups to complete said chip wiring.

6. The method of claim 4 after step (f) when a task completes wiring its assigned bay group and becomes idle, further comprising the steps of:

(g) assessing the degree of completion of each of the remaining wiring tasks in wiring its assigned bay group;

(h) selecting the wiring task that has the lowest degree of completion;

(i) creating a new bay group by subdividing said bay group assigned to said selected wiring task;

(j) assigning said new bay group to the idle task;

(k) repeating step (d); and

(1) repeating steps (g) through (k) until all bay groups have been wired.

7. The method of claim 6 further comprising the step of merging said wiring of said bay groups to complete said chip wiring.

8. The method of claim 1 wherein each of said bays covers a generally rectangular area of said integrated circuit chip,

said bays comprise an array of parallel rectangular areas spanning an entire dimension selected from the length and width of the integrated circuit chip, and

said bay groups comprise larger parallel rectangular areas spanning an entire dimension selected from the length and width of the integrated circuit chip.

9. The method of claim 1 wherein said bays include relatively horizontal bays and relatively vertical bays.

10. The method of claim 9 wherein all steps are performed twice, once for said relatively horizontal bays, and once for said relatively vertical bays.

11. A method for performing a plurality of wiring tasks for wiring areas on an integrated circuit chip in a parallel process of wiring, comprising the steps of:

(a) dividing said chip into a plurality of parallel slices spanning an entire dimension of a length or width of a chip, and dividing each said slice into parallel rectangular bays spanning an entire dimension of a length or width of a chip, said bays including rough wiring coordinates,

(b) grouping said rectangular bays into a plurality of bay groups, each of said bay groups containing a contiguous group of bays including a non-edge bay and at least one edge bay adjacent another bay group,

(c) assigning each successive bay group to be wired in a different one of said wiring tasks, and

(d) each of said wiring tasks including performing of wiring of said bays in a bay group assigned thereto according to said rough wiring coordinates and performing said wiring in parallel with performance of said other wiring tasks,

(1) if wiring an edge bay, before wiring begins checking edge bays status as to whether said adjacent edge bay has been wired, whether said adjacent edge bay is currently being wired, and whether said adjacent edge bay is as yet unwired, and

(i) if said adjacent edge bay has been wired, wiring said edge bay in accordance with said adjacent edge bay wiring, or

(ii) if said adjacent edge bay is currently being wired, waiting for said adjacent edge bay to finish being wired and then wiring said edge bay in accordance with said adjacent edge bay wiring, or

(iii) if said adjacent edge bay is as yet unwired, wiring said edge bay, and otherwise,

(2) wiring said non-edge bay.

12. The method of claim 11 wherein each wiring task controlled by a respective computer processor.

13. The method of claim 12 wherein said wiring of said edge bay in accordance with said adjacent edge bay is performed by accessing a database of detailed wiring data for said plurality of bays.

14. The method of claim 11 further comprising the steps of:

(e) assigning a next available unwired bay group to a task that has completed wiring its assigned bay group, and

(f) repeating steps (d) and (e) until all unwired bay groups have been assigned to wiring tasks.

15. The method of claim 14 further comprising the step of merging said wiring of said bay groups to complete said chip wiring.

16. The method of claim 14 further comprising:

(g) after step (f) upon completion of wiring of bay groups assigned to a task thereby rendering said task idle, performing the further steps comprising;

(1) assessing the degree of completion of each of said remaining wiring tasks in wiring its assigned bay group,

(2) selecting a low completion wiring task that has the lowest degree of completion,

(3) creating a new bay group by subdividing said bay group assigned to said low completion wiring task,

(4) assigning said new bay group to said idle task,

(5) repeating step (4), and

(6) repeating steps (g) (1) through (g) (5) until all bay groups have been wired.

17. The method of claim 16 further comprising the step of merging the wiring of the bay groups to complete the chip wiring.

18. The method of claim 11 wherein

said bays comprise an array of parallel rectangular areas spanning an entire dimension selected from the length and width of the integrated circuit chip, and

said bay groups comprise larger parallel rectangular areas spanning an entire dimension selected from the length and width of the integrated circuit chip.

19. The method of claim 11 wherein the bays are selected from the group consisting of relatively horizontal bays and relatively vertical bays.

20. The method of claim 19 wherein all steps are performed twice, once for the relatively horizontal bays, and once for the relatively vertical bays.

21. A method for performing a plurality of wiring tasks for wiring areas on an integrated circuit chip in a parallel process of wiring, comprising the steps of:

(a) dividing said chip into a plurality of parallel slices spanning an entire dimension of a length or width of a chip, and dividing each of said slices into parallel rectangular bays spanning an entire dimension of a length or width of a chip, said bays including rough wiring coordinates,

(b) grouping said rectangular bays into a plurality of bay groups, each said bay group containing a contiguous group of bays including a non-edge bay and at least one edge bay adjacent another bay group,

(c) assigning each successive bay group to be wired in a different one of said wiring tasks, and

(d) each of said wiring tasks including performing of wiring of said bays in a bay group assigned thereto according to said rough wiring coordinates and performing said wiring in parallel with performance of said other wiring tasks,

(1) if wiring an edge bay, before wiring begins checking edge bays status as to whether said adjacent edge bay has been wired, whether said adjacent edge bay is currently being wired, and whether said adjacent edge bay is as yet unwired, and

(i) if said adjacent edge bay has been wired, wiring said edge bay in accordance with said adjacent edge bay wiring, or

(ii) if said adjacent edge bay is currently being wired, waiting for said adjacent edge bay to finish being wired and then wiring said edge bay in accordance with said adjacent edge bay wiring, or

(iii) if said adjacent edge bay is as yet unwired, wiring said edge bay, and otherwise,

(2) wiring said non-edge bay,

(e) assigning a next available unwired bay group to a task that has completed wiring its assigned bay group, and

(f) repeating steps (d) and (e) until all unwired bay groups have been assigned to wiring tasks,

(g) after step (f), upon completion of wiring of bay groups assigned to a task, thereby rendering said task idle, performing the further steps comprising;

(1) assessing the degree of completion of each of said remaining wiring tasks in wiring its assigned bay group,

(2) selecting a low completion wiring task that has the lowest degree of completion,

(3) creating a new bay group by subdividing said bay group assigned to said low completion wiring task,

(4) assigning said new bay group to said idle task,

(5) repeating step (d), and

(6) repeating steps (g) (1) through (g) (5) until all bay groups have been wired.

22. The method of claim 21 further comprising the step of merging said wiring of said bay groups to complete said chip wiring.

23. The method of claim 21 wherein

said bays comprise an array of parallel rectangular areas spanning an entire dimension selected from the length and width of the integrated circuit chip and

said bay groups comprise larger parallel rectangular areas spanning an entire dimension selected from the length and width of the integrated circuit chip.

24. The method of claim 21 wherein the bays are selected from the group consisting of relatively horizontal bays and relatively vertical bays.

25. The method of claim 24 wherein all steps are performed twice, once for the relatively horizontal bays, and once for the relatively vertical bays.

26. A method for performing a plurality of wiring tasks for wiring areas on an integrated circuit chip in a parallel process of wiring, comprising the steps of:

(a) dividing said chip into a plurality of parallel slices spanning an entire dimension of selected from the length and the width of a chip, and dividing each of said slices into parallel rectangular bays, said bays spanning an entire dimension selected from the length and the width of a chip, each of said bays covering a generally rectangular area of the integrated circuit chip, said bays including rough wiring coordinates,

(b) grouping said rectangular bays into a plurality of bay groups, each said bay group containing a contiguous group of bays including a non-edge bay and at least one edge bay adjacent another bay group,

(c) assigning each successive bay group to be wired in a different one of said wiring tasks, and

(d) each of said wiring tasks including performing of wiring of said bays in a bay group assigned thereto according to said rough wiring coordinates and performing said wiring in parallel with performance of said other wiring tasks wherein each of said wiring tasks is controlled by a respective computer processor, and

(1) if wiring an edge bay, before wiring begins checking edge bays status as to whether said adjacent edge bay has been wired, whether said adjacent edge bay is currently being wired, and whether said adjacent edge bay is as yet unwired, and

(i) if said adjacent edge bay has been wired, wiring said edge bay in accordance with said adjacent edge bay wiring, or

(ii) if said adjacent edge bay is currently being wired, waiting for said adjacent edge bay to finish being wired and then wiring said edge bay in accordance with said adjacent edge bay wiring, or

(iii) if said adjacent edge bay is as yet unwired, wiring said edge bay in accordance with said adjacent edge bay by accessing a database of detailed wiring data for said plurality of bays, and otherwise,

(2) wiring said non-edge bay,

(e) assigning a next available unwired bay group to a task that has completed wiring its assigned bay group,

(f) repeating steps (d) and (e) until all unwired bay groups have been assigned to wiring tasks,

(g) after step (f) upon completion of wiring of bay groups assigned to a task thereby rendering said task idle, performing the further steps comprising;

(1) assessing the degree of completion of each of said remaining wiring tasks in wiring its assigned bay group,

(2) selecting a low completion wiring task that has the lowest degree of completion,

(3) creating a new bay group by subdividing said bay group assigned to said low completion wiring task,

(4) assigning said new bay group to said idle task,

(5) repeating step (d), and

(6) repeating steps (g) (1) through (g) (5) until all bay groups have been wired,

(h) all steps are performed twice, once for the relatively horizontal bays, and once for the relatively vertical bays, and

(i) merging said wiring of said bay groups to complete said chip wiring.