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Random access memory cell resistant to radiation induced upsets

  • US 5,631,863 A
  • Filed: 01/16/1996
  • Issued: 05/20/1997
  • Est. Priority Date: 02/14/1995
  • Status: Expired due to Term
First Claim
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1. A CMOS memory cell, comprising:

  • a first P-channel FET device connected between a first storage node and a relatively positive voltage and a first N channel FET device connected between said first storage node and a relatively negative voltage, with the gates of said first P channel and said first N channel devices connected in common at a first gate node and with said first storage node selectively connected to a first output line by a word line signal;

    a second P-channel FET device connected between a second storage node and said relatively positive voltage and a second N channel FET device connected between said second storage node and said relatively negative voltage, with the gates of said second P channel and said second N channel devices connected in common at a second gate node and with said second storage node selectively connected to a second output line by said word line signal; and

    at least a first coupling means having a first terminal connected to said word line signal, a second terminal connected to said first storage node, a third terminal connected to said second gate node, and a first body isolated from said relatively positive voltage and said relatively negative voltage, said first coupling means further having a first resistive means connected between said first coupling means second terminal and said first body, and a second resistive means connected between said first coupling means third terminal and said first body.

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