Random access memory cell resistant to radiation induced upsets

• US 5,631,863 A
• Filed: 01/16/1996
• Issued: 05/20/1997
• Est. Priority Date: 02/14/1995
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Dougal, Gregor D., Fechner, Paul S., Golke, Keith W.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/587,065
• Time in Patent Office: 490 Days
• Field of Search: 365/156, 365/154, 365/148, 365/190, 257/393, 257/903, 257/904
• US Class Current: 365/156
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

A radiation resistant random access memory cell which has a coupling circuit between a storage node of a first CMOS pair and a gate node of a second CMOS pair. The coupling circuit is controlled by a word line and provides a first resistive element between the storage node and the body of the coupling circuit and a second resistive element between the gate node and the body of the coupling circuit.

Claims

1. A CMOS memory cell, comprising:

a first P-channel FET device connected between a first storage node and a relatively positive voltage and a first N channel FET device connected between said first storage node and a relatively negative voltage, with the gates of said first P channel and said first N channel devices connected in common at a first gate node and with said first storage node selectively connected to a first output line by a word line signal;

a second P-channel FET device connected between a second storage node and said relatively positive voltage and a second N channel FET device connected between said second storage node and said relatively negative voltage, with the gates of said second P channel and said second N channel devices connected in common at a second gate node and with said second storage node selectively connected to a second output line by said word line signal; and

at least a first coupling means having a first terminal connected to said word line signal, a second terminal connected to said first storage node, a third terminal connected to said second gate node, and a first body isolated from said relatively positive voltage and said relatively negative voltage, said first coupling means further having a first resistive means connected between said first coupling means second terminal and said first body, and a second resistive means connected between said first coupling means third terminal and said first body.

2. The CMOS memory cell of claim 1 wherein said first resistive means has a resistance value sufficiently low to maintain a first voltage value between said first coupling means second terminal and said first body below a value which would initiate a first lateral bipolar transistor action, and said second resistive means has a resistance value sufficiently high to prevent discharge of said second gate node following a discharge of said first storage node.

3. The CMOS memory cell of claim 1 wherein each of said first and second resistive means comprises a resistive Schottky device.

4. The CMOS memory cell of claim 3 wherein said resistive schottky device comprises a TiSi₂ Schottky device.

5. The CMOS memory cell of claim 2 wherein said first and second resistive means have a resistance value sufficiently low to allow said first gate node to charge up in a first time thereby limiting crowbar current.

6. The CMOS memory cell of claim 5 wherein said first and second resistive means are immune to total dose radiation.

7. The CMOS memory cell of claim 1 further comprising:

a second coupling means having a first terminal connected to said word line signal, a second terminal connected to said second storage node, a third terminal connected to said first gate node, and a second body isolated from said relatively positive voltage and said relatively negative voltage, said second coupling means further having a third resistive means connected between said second coupling means second terminal and said second body, and a fourth resistive means connected between said second coupling means third terminal and said second body.

8. A CMOS memory cell comprising:

a first inverter having a first input and a first output, said first output selectively coupled to a first output line;

a second inverter having a second input and a second output, said second output connected to said first input and selectively coupled to a second output line; and

a first transistor having a first terminal connected to a word line signal, a second terminal connected to said first output, a third terminal connected to said second input, and an isolated body, said first transistor having a first resistive means between said second terminal and said isolated body and a second resistive means between said third terminal and said isolated body.

9. The CMOS memory cell of claim 8 wherein said first resistive means has a resistance value sufficiently low to maintain a first voltage value between said second terminal and said isolated body below a value which would initiate a lateral bipolar transistor action and said second resistive means has a resistance value sufficiently high to prevent discharge of said second input following a discharge of said first output.