Test circuit and test method of integrated semiconductor device

• US 5,631,913 A
• Filed: 02/08/1995
• Issued: 05/20/1997
• Est. Priority Date: 02/09/1994
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Maeda, Toshinori
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/385,658
• Time in Patent Office: 832 Days
• Field of Search: 371/22.4, 371/22.5, 371/25.1, 371/21.1, 371/27, 371/22.3, 371/22.6, 324/158 R, 324/73.1, 365/201
• US Class Current: 714/732
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/40 using compression techniques

Abstract

In a test circuit of an integrated semiconductor device such as a memory, a parallel-input linear feedback shift register (LFSR) is used for both compressing data and comparing the obtained compressed value with an expected compressed value, thereby judging whether or not the integrated semiconductor device under test is normal. The parallel-input LFSR comprises a plurality of registers, a plurality of 2-input exclusive-OR gates placed in the stages previous to the respective registers mentioned above, and a feedback information generating means for generating feedback information from the output from the final-stage register and from the output from the register in a specified middle stage. In testing the integrated semiconductor device, the parallel-input LFSR compresses sequential sets of data from the integrated semiconductor device so as to obtain a compressed signature and then supplies the first input of the 2-input exclusive-OR gate placed in the leftmost position with the output from the final-stage register, while supplying the first inputs of the other exclusive-OR gates with the outputs from the registers in their respective previous stages. The second input of each of the exclusive-OR gates is supplied with an expected signature. Thus, the compressed value is compared with the expected compressed value at the respective exclusive-OR gates of the parallel-input LFSR.

Claims

1. A test circuit for testing an integrated semiconductor device, said test circuit comprising:

means for storing an expected compressed value;

a calculating circuit for compressing sequential sets of parallel data and obtaining a compressed value and also, for comparing said expected compressed value with a compressed value obtained from said sequential sets of parallel data;

an information collecting means for supplying, to said calculating circuit, sequential sets of parallel data obtained from an integrated semiconductor device under test and for supplying to said calculating circuit the compressed valued obtained by said calculating means and the expected compressed value stored in said expected compressed value storing means,

wherein said calculating circuit functions as a comparing means for comparing said obtained compressed value with the expected compressed value, and also for compressing data from said integrated semiconductor device under test during a normal operation of the integrated semiconductor device.

2. The test circuit according to claim 1,

wherein said calculating circuit and said information collecting means form a parallel-input linear feedback shift register.

3. The test circuit according to claim 2,

wherein the parallel-input linear feedback shift register comprises:

a plurality of registers;

a plurality of 2-input exclusive-OR gates placed in the stages previous to said respective registers; and

a feedback information generating means for generating feedback information from the output of the register in the final stage and from the output of the register in a specified middle stage, each of said registers receiving the output from the 2-input exclusive-OR gate in its previous stage, the first input of each of the 2-input exclusive-OR gates except the 2-input exclusive-OR gate placed in the stage previous to the register in the first stage being supplied with the output from the register in its previous stage, the first input of the 2-input exclusive-OR gate placed in the stage previous to the register in the first stage being supplied with the output from a feedback information selecting means,

the calculating circuit is composed of the plurality of 2-input exclusive-OR gates provided in said parallel-input linear feedback shift register,

the information collecting means consists of;

a feedback information selecting means for selecting, based on a control signal, either the output from the feedback information generating means or the output from the register in the final stage of said parallel-input linear feedback shift register; and

an input selecting means for selecting, based on the control signal, either the parallel data or the expected compressed value stored in the expected compressed value storing means as data to be supplied to the second input of each of the registers of said parallel-input linear feedback shift register.

4. The test circuit according to claim 1, 2, or 3,

wherein the integrated semiconductor device to be tested is a memory.

5. The test circuit according to claim 1, 2, or 3,

wherein the integrated semiconductor device to be tested is an internal functional block.

6. The test circuit according to claim 3,

wherein the input selecting means is composed of a 2-input multiplexer.

7. The test circuit according to claim 3,

further comprising a single data bus,

wherein each of the 2-input exclusive-OR gates of the parallel-input linear feedback shift register is connected directly to said data bus, while the integrated semiconductor device and the expected compressed value storing means are connected to said data bus via their respective output buffers, and

the input selecting means is comprised of a control circuit for controlling the respective output buffers of said integrated semiconductor device and of said expected compressed value storing means so that either one of the sets of data from said integrated semiconductor device and from said expected compressed value storing means is outputted to said data bus.

8. The test circuit according to claim 7,

wherein a plurality of integrated semiconductor devices are connected to the data bus.

9. The test circuit according to claim 3 or 7,

wherein based on the control signal, the input selecting means selects the parallel data from the integrated semiconductor device in a compression cycle for compressing the parallel data from the integrated semiconductor device, while it selects the expected compressed value from the expected compressed value storing means for comparing the obtained compressed value with the expected compressed value for judging integrated semiconductor device.

10. The test circuit according to claim 3,

wherein the expected compressed value storing means preliminarily rotates the expected compressed value by 1 bit in the shifting direction of the parallel-input linear feedback shift register and then stores it.

11. The test circuit according to claim 3,

further comprising a single data bus,

wherein the parallel-input linear feedback shift register comprises an output buffer for connecting the outputs from the individual registers and the output from the feedback information selecting means to said data bus so that the first input of each of the 2-input exclusive-OR gates is connected directly to said data bus, that the first input of each of the 2-input exclusive-OR gates except the 2-input exclusive-OR gate placed in the stage previous to the register in the first stage is supplied with the output from the register in its previous stage via said output buffer and via said data bus, and that the first input of the 2-input exclusive-OR gate placed in the stage previous to the register in the first stage is supplied with the output from said feedback information selecting means via said output buffer and via said data bus.

12. The test circuit according to claim 11,

further comprising an additional data bus,

wherein the parallel input linear feedback shift register comprises an additional output buffer for connecting the outputs from the individual registers and the output from the feedback information selecting means to said additional data bus so that the second input of each of the 2-input exclusive-OR gates is connected directly to said data bus, that the second input of each of the 2-input exclusive-OR gates except the 2-input exclusive-OR gate placed in the stage previous to the register in the first stage is supplied with the output from the register in its previous stage via said additional output buffer and said additional data bus, and that the second input of the 2-input exclusive-OR gate placed in the stage previous to the register in the first stage is supplied with the output from said feedback information selecting means via said additional output buffer and via said additional data bus.

13. The test circuit according to claim 12,

wherein the integrated semiconductor device and the expected compressed value storing means are connected to each of the data bus and additional data bus,

each of said integrated semiconductor devices and expected compressed value storing means is internally provided with an output buffer, and

the input selecting means is composed of a control circuit for controlling the output buffers provided in said integrated semiconductor device and in the expected compressed value storing means, respectively, and the output buffers provided in said parallel-input linear feedback shift register so that either one of the two data buses is used for compression using the parallel-input linear feedback shift register, while data is outputted onto the other data bus from either one of the integrated semiconductor device and expected compressed value storing means which are connected to the other data bus.

14. The test circuit according to claim 12,

wherein the integrated semiconductor device is connected to each of the data bus and additional data bus,

each of said integrated semiconductor devices is internally provided with an output buffer,

the input selecting means is composed of a control circuit for controlling the output buffers provided in said integrated semiconductor devices, respectively, and the output buffers provided in said parallel-input linear feedback shift register so that a set of data is outputted onto one of the data buses from the integrated semiconductor device connected to one of the data buses, while another set of data is outputted onto the other data bus from the integrated semiconductor device connected to the other data bus, the two sets of data outputted onto said two data buses being compared with each other at the 2-input exclusive-OR gates of the parallel-input linear feedback shift register.

15. The test circuit according to claim 3 or 7, further comprising,

a normal/abnormal judging means for receiving, as its inputs, the outputs from the 2-input exclusive-OR gates of the parallel-input linear feedback shift register, judging whether or not the integrated semiconductor device is normal from the values of the inputs, and outputting the result of judgment.

16. The test circuit according to claim 3 or 7, further comprising,

a diagnostic register for receiving, as its inputs, the outputs from the 2-input exclusive-OR gates of the parallel-input linear feedback shift register and storing the contents of the inputs, while outputting the contents of the inputs.

17. The test circuit according to claim 7,

wherein scan-in information is inputted to the feedback information selecting means,

said feedback information selecting means selects said scan-in information in scanning operation, and

the output from the register in the final stage of the parallel-input linear feedback shift register is connected as scan-out information to a scan path,

said test circuit further comprising,

a zero output means for supplying zero as the parallel data to each of the registers of said parallel-input linear feedback shift register in the scanning operation so that the outputs from all the registers of said parallel-input linear feedback shift register can be observed from the outside.

18. The test circuit according to claim 14, further comprising,

a normal/abnormal judging means for receiving the result of comparing the two sets of data at the 2-input exclusive-OR gates of the parallel-input linear feedback shift register, judging whether or not the two sets of data match, and outputting the result of judgment.

19. A method for testing an integrated semiconductor device, comprising the steps of:

repeatedly compressing sequential sets of parallel data by reading sequential sets of data from the integrated semiconductor device in accordance with the same sequential addresses as supplied in generating an expected compressed value that has previously been obtained, while inputting the sequential sets of read data in parallel to the individual registers of a parallel-input linear feedback shift register, and shifting the sets of inputted data, so that the outputs from the individual registers at the time of compressing the final set of parallel data are obtained as the compressed value of the parallel data;

then supplying the first input of a 2-input exclusive-OR gate placed in the stage previous to the register in the first stage with the output from the register in the final stage and supplying the first inputs of 1-input exclusive-OR gates placed in the stages previous to the respective registers except the register in the first stage with the outputs from the registers in their respective previous stages;

inputting the expected compressed value to the second input of each of the 2-input exclusive-OR gates of said parallel-input linear feedback shift register; and

comparing the compressed value of the parallel data with the expected compressed value bit by bit correspondingly at the 2-input exclusive-OR gates and judging, based on the result of comparison, whether or not the integrated semiconductor device under test is normal.

20. The method of testing according to claim 19,

wherein any one of a plurality of integrated semiconductor devices is connected to a single data bus via an output buffer, sequential sets of data are read from the connected integrated semiconductor device via said data bus, the sequential sets of read data are compressed so as to obtain the compressed value, the obtained compressed value is compared with the expected compressed value,

another one of the plurality of integrated semiconductor devices is connected to the data bus via the output buffer, sequential sets of data are read from the connected integrated semiconductor device via said data bus, the sequential sets of read data are compressed so as to obtain the compressed value, and the obtained compressed value is compared with the expected compressed value,

said procedures being repeatedly performed until the testing of all the integrated semiconductor devices is completed.

21. The method of testing according to claim 19,

wherein while repeatedly compressing the sequential sets of data from the integrated semiconductor device by means of the parallel-input linear feedback shift register, each time the sequential sets of data are compressed, middle compression information consisting of the output from any one of the registers except the register in the final stage of said parallel-input linear feedback shift register and of feedback information is stored or inputted, via a data bus, as test data for the integrated semiconductor device connected to the data bus.

22. The method of testing according to claim 19,

wherein an initial value is scanned in to the parallel-input linear feedback shift register before initiating a test.

23. The method of testing according to claim 22,

wherein the integrated semiconductor device to be tested is composed of a plurality of memories,

said memories have different capacities and different data to be written or having been written therein, and

the initial value to be scanned in to the parallel-input linear feedback shift register has been previously obtained so as to equalize the expected compressed values obtained by reading the respective sequential sets of data from said memories.

24. The method of testing according to claim 22,

wherein the integrated semiconductor device to be tested is composed of a plurality internal functional blocks, said internal functional blocks having different functions or different sequential inputs to be supplied thereto, and

the initial value to be scanned in to the parallel-input linear feedback shift register has been previously obtained so as to equalize the expected compressed values obtained from the respective outputs from the internal functional blocks corresponding to said respective sequential inputs.