Circuit and method of encrypting key validation

• US 5,631,962 A
• Filed: 10/23/1995
• Issued: 05/20/1997
• Est. Priority Date: 10/23/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Balph, Thomas J., Millman, Steven D.
• Primary Examiner(s): Cain, David C.
• Application Number:
  US08/547,005
• Time in Patent Office: 575 Days
• Field of Search: 380/23, 380/24, 380/25, 380/4, 380/49, 380/46, 380/30, 380/28
• US Class Current: 713/170
• CPC Class Codes: G07C 2009/00222 by more than one push button
• CPC Class Codes: G07C 2009/00412 the transmitted data signal being encrypted
• CPC Class Codes: G07C 2009/00507 keyless data carrier having more than one function
• CPC Class Codes: G07C 2009/00769 with data transmission performed by wireless means
• CPC Class Codes: G07C 9/00309 operated with bidirectional data transmission between data carrier and locks
• CPC Class Codes: H04L 2209/04 Masking or blinding
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/805 Lightweight hardware, e.g. radio-frequency identification [RFID] or sensor
• CPC Class Codes: H04L 2209/84 Vehicles
• CPC Class Codes: H04L 9/3228 One-time or temporary data, i.e. information which is sent for every authentication or authorization, e.g. one-time-password, one-time-token or one-time-key
• CPC Class Codes: H04L 9/3271 using challenge-response

Abstract

An electronic key validation process increases security by encrypting the security access codes. A key (10) receives data having a hidden polynomial select code and polynomial seed from a host (12). A locally stored (24, 26) select offset and seed offset in the key identifies the location (22) of the select code and seed in the data. The select code decodes (32) into polynomial coefficients which are used to configure a polynomial generator (34). The seed is loaded into the polynomial generator as a starting point of the polynomial. The polynomial generator is clocked a number of cycles to calculate a remainder. The select code is modified (28) to select a new polynomial, and the polynomial generator is clocked another number of cycles. The host runs a similar encryption algorithm. The remainder is sent to the host where it is compared with the host generated remainder for key validation.

Claims

1. A method of validating a key with a host, comprising the steps of:

configuring a polynomial generator with a first polynomial;

clocking said polynomial generator a first number of cycles based on a first clock count from a starting point to calculate a first remainder in said polynomial generator;

configuring said polynomial generator with a second polynomial; and

clocking said polynomial generator a second number of cycles based on a second clock count from said first remainder to calculate a second remainder in said polynomial generator.

2. The method of claim 1 further comprising the steps of:

configuring a polynomial generator in the host with said first polynomial;

clocking said polynomial generator in the host a first number of cycles based on a first clock count from a starting point to calculate a first remainder in said polynomial generator in the host;

configuring said polynomial generator in the host with said second polynomial; and

clocking said polynomial generator in the host a second number of cycles based on a second clock count from said first remainder to calculate a second remainder in said polynomial generator in the host.

3. The method of claim 1 further comprising the steps of:

receiving a first polynomial select code and a polynomial seed; and

selecting said first polynomial based on said first polynomial select code.

4. The method of claim 3 further including the steps of:

adding a first value to said first polynomial select code for providing a second polynomial select code; and

selecting said second polynomial based on said second polynomial select code.

5. The method of claim 4 further including the steps of:

waiting for a maximum count before further clocking said polynomial generator in the key;

adding a second value to said second polynomial select code for providing a third polynomial select code; and

waiting for said maximum count before further clocking said polynomial generator in the key.

6. The method of claim 5 further including the steps of:

selecting a third polynomial based on said third polynomial select code;

configuring said polynomial generator in the key with said third polynomial; and

configuring said polynomial generator in the host with said third polynomial.

7. The method of claim 6 further including the steps of:

clocking said polynomial generator in the key a third number of cycles from said second remainder to calculate a third remainder in said polynomial generator in the key, where said third number of cycles is equal to a sum of said first number of cycles and said second number of cycles; and

clocking said polynomial generator in the host said third number of cycles from said second remainder to calculate a third remainder in said polynomial generator in the host.

8. The method of claim 7 further including the steps of:

sending said third remainder to the host as a key validation code; and

comparing said key validation code with said third remainder in said polynomial generator in the host to determine validation of the key.

9. The method of claim 1 further including the step of embedding a first polynomial select code and a polynomial seed in a data field in locations defined by a select offset and a seed offset respectively.

10. An integrated circuit for encrypting a key validation, comprising:

a first register coupled for receiving data and a select offset and a seed offset where said select offset identifies a polynomial select code within said data and said seed offset identifies a polynomial seed within said data;

a select decode logic circuit coupled for receiving said polynomial select code for providing a polynomial;

a polynomial generator coupled for receiving said polynomial from said select decode logic circuit and further coupled for receiving said polynomial seed for defining a starting point of said polynomial, said polynomial generator being clocked a first number of cycles to calculate a remainder in said polynomial generator; and

a modification circuit having a first input coupled for receiving said polynomial select, and an output for providing an updated polynomial select code to said select decode logic circuit.

11. The integrated circuit of claim 10 wherein said polynomial generator comprises:

a plurality of cells serially coupled with each cell receiving one bit of said polynomial and one bit of said polynomial seed; and

a first flip-flop having a data input coupled for receiving a feedback signal from a last one of said plurality of cells, a clock input coupled for receiving a clock signal, and an output coupled to a first one of said plurality of cells.

12. The integrated circuit of claim 11 wherein said last one of said plurality of cells includes:

a logic gate having a first input coupled for receiving said feedback signal, and a second input coupled to an output of an adjacent one of said plurality of cells;

a multiplexer having a first input coupled to an output of said logic gate, a second input coupled to said output of said adjacent one of said plurality of cells, and a control input coupled for receiving said one bit from said polynomial; and

a second flip-flop having a data input coupled to an output of said multiplexer, a clock input coupled for receiving said clock signal, and an output for providing said feedback signal.

13. The integrated circuit of claim 12 wherein said polynomial generator further includes:

a second register storing a count select;

a counter decode logic circuit coupled for receiving said count select and providing a count value; and

a counter coupled for receiving said count value and providing a number of clock signals equal to said count value.

14. A method of encrypting a validation sequence in an integrated circuit between a key and a host, comprising the steps of:

receiving data from a host where said data includes a 5 first polynomial select code and a polynomial seed;

decoding said first polynomial select code into a first polynomial;

configuring a polynomial generator with said first polynomial;

loading said polynomial generator with said polynomial seed as a starting point of said first polynomial;

clocking said polynomial generator a first number of cycles based on a first clock count from said starting point to calculate a first remainder in said polynomial generator;

configuring said polynomial generator with a second polynomial; and

clocking said polynomial generator a second number of cycles based on a second clock count from said first remainder to calculate a second remainder in said polynomial generator.

15. The method of claim 14 further comprising the steps of:

configuring a polynomial generator in the host with said first polynomial;

clocking a polynomial generator in the host a first number of cycles based on a first clock count from a starting point to calculate a first remainder in said polynomial generator in the host;

configuring said polynomial generator in the host with said second polynomial; and

clocking said polynomial generator in the host a second number of cycles based on a second clock count from said first remainder to calculate a second remainder in said polynomial generator in the host.

16. The method of claim 15 further including the steps of:

waiting for a maximum count before further clocking said polynomial generator in the key;

adding a first value to said first polynomial select code for providing a second polynomial select code; and

decoding said second polynomial select code into said second polynomial.

17. The method of claim 16 further including the steps of:

waiting for said maximum count before further clocking said polynomial generator in the key;

adding a second value to said second polynomial select code for providing a third polynomial select code;

decoding said third polynomial select code into a third polynomial; and

configuring said polynomial generator in the key with said third polynomial.

18. The method of claim 17 further including the steps of:

clocking said polynomial generator in the key a third number of cycles from said second remainder to calculate a third remainder in said polynomial generator in the key, where said third number of cycles is equal to a sum of said first number of cycles and said second number of cycles;

configuring said polynomial generator in the host with said third polynomial; and

clocking said polynomial generator in the host a third number of cycles from said second remainder to calculate a third remainder in said polynomial generator in the host, where said third number of cycles is equal to a sum of said first number of cycles and said second number of cycles.

19. The method of claim 18 further including the steps of:

sending said third remainder to the host as a key validation code; and

comparing said key validation code with said third remainder in said polynomial generator in the host to determine validation of the key.

20. The method of claim 14 further including the step of embedding said first polynomial select code and a polynomial seed in a data field in locations defined by a select offset and a seed offset respectively.