Multi-segmented bus and method of operation

• US 5,632,029 A
• Filed: 05/23/1995
• Issued: 05/20/1997
• Est. Priority Date: 03/06/1990
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Bruce, Richard H., Gastinel, Jean, Gunning, William F., Overton, Michael
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Walker, Tyrone V.
• Application Number:
  US08/449,398
• Time in Patent Office: 728 Days
• Field of Search: 395/375, 395/500, 395/775, 395/800, 395/306, 395/307, 395/308, 395/309, 395/310, 437/195
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438

Abstract

A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

Claims

1. A method of segmented shared bus communication comprising:

providing at least a first-level bus segment, at least first and second second-level bus segments, and a third-level bus segment, wherein two of the first-level, first second-level, and third level bus segments have differing electrical characteristics;

providing a first-level interface chip for connecting said first-level bus segment with said first second-level bus segment;

providing at least first and second second-level interface chips for connecting said first and second second-level bus segments, respectively, with said third-level bus segment;

transmitting data over said first-level bus segment to said first-level interface chip and holding said data in said first-level interface chip, said transmitting and holding occurring during a first bus cycle having a first period;

receiving said data from said first-level interface chip on said first second-level bus segment, transmitting said data over said first second-level bus segment to said first second-level interface chip and holding said data in said first second-level interface chip, said receiving, transmitting and holding occurring during a second bus cycle having a second period substantially equal to said first period; and

receiving said data from said first second-level interface chip on said third-level bus segment, transmitting said data over said third-level bus segment and holding said data in said second second-level interface chip, said receiving, transmitting and holding occurring during a third bus cycle having a third period substantially equal to said first period.

2. The method of claim 1, wherein said step of transmitting data over said first-level bus segment includes transmitting said data over a first unidirectional portion of said first-level bus, and further comprising:

transmitting data over a second unidirectional portion of said first-level bus segment from said first-level interface chip simultaneously with said transmission over said first unidirectional portion.

3. The method of claim 1, wherein the voltage level used to represent a logic level on one of the two bus segments having differing electrical characteristics is different from the voltage level used to represent the logic level on the other of the two bus segments having differing electrical characteristics.

4. The method of claim 1, wherein:

said first-level bus segment is a board bus;

said second-level bus segments are MCC buses; and

said third-level bus segment is a backplane bus.

5. A method of segmented shared bus communication comprising:

providing a plurality of first-level bus segments, a plurality of second-level bus segments and at least a first third-level bus segment;

providing a plurality of integrated circuit chips connected to said first-level bus segments;

providing a plurality of first-level interface chips for connecting said first-level bus segments with said second-level bus segments;

providing a plurality of second-level interface chips for connecting said second-level bus segments with said third-level bus segment;

transmitting data from a first of said integrated circuits over a first first-level bus segment to a first first-level interface chip and holding said data in said first first-level interface chip;

receiving said data from said first first-level interface chip on a first second-level bus segment, transmitting said data over said first second-level bus segment to a first second-level interface chip and holding said data in said first second-level interface chip;

receiving said data from said first second-level interface chip on said third-level bus segment, transmitting said data over said third-level bus segment and holding said data in said plurality of second-level interface chips;

receiving said data from said plurality of second-level interface chips on said plurality of second-level bus segments and holding said data in said plurality of first-level interface chips; and

receiving said data from said plurality of first-level interface chips on said plurality of first-level bus segments, transmitting said data over said plurality of first-level bus segments and receiving said data substantially simultaneously in all of said plurality of said integrated circuit chips.

6. The method of claim 5, wherein said step of transmitting data over said first first-level bus segment includes transmitting said data over a first unidirectional portion of said first first-level bus segment, and further comprising:

transmitting data over a second unidirectional portion of said first-level bus segment from said first-level interface chip and receiving in one of said integrated circuit chips simultaneously with said transmission over said first unidirectional portion.

7. In a synchronous segmented shared bus system having at least first and second bus segments, a circuit board comprising:

a board base;

a plurality of traces forming said second bus segment formed in said board base lying substantially in a plane;

at least a first multi-chip carrier mounted on said board base which includes;

a substrate having first and second edges and first and second faces;

a plurality of conductive traces formed on said substrate and forming said first bus segment;

a plurality of integrated circuits positioned on said first face of said substrate and coupled to said first bus segment; and

at least first and second bus interface chips for receiving data from said first bus segment, holding said data and transmitting said data to said second bus segment, said first and second bus interface chips positioned on said substrate adjacent said first and second edges;

said second bus segment extending beneath said multi-chip carrier mounted on said board substantially between said first and second bus interface chips.

8. The circuit board of claim 7, wherein said first multi-chip carrier provides an output to said second bus segment having a first voltage and a first capacitance, and further comprising:

a second multi-chip carrier coupled to said second bus segment, said second multi-chip carrier providing an output to said second bus segment having a voltage substantially equal to said first voltage and a capacitance substantially equal to said first capacitance.

9. The circuit board of claim 7, wherein said second bus segment has a length of less than about 15 inches.

10. The circuit board of claim 7, wherein said substrate lies substantially in a plane parallel to said second bus segment.

11. The circuit board of claim 7, further comprising:

a plurality of cooling fins positioned on the second face of said substrate.

12. The circuit board of claim 7, further comprising:

connector means for conductively connecting said first and second bus interface chips to said second bus segment, said connector means having a length less than about 2 mm.

13. The circuit board of claim 7, wherein said first bus segment is formed without a terminal load resistor.

14. The circuit board of claim 7, wherein:

said first bus segment includes a first unidirectional portion for providing data from one of said integrated circuits to said second bus segment and a second unidirectional portion for providing data from said second bus segment to one of said integrated circuits.

15. The circuit board of claim 7, wherein the synchronous segmented shared bus system has a third bus segment, the multi-chip carrier further comprising:

at least a third bus interface chip for receiving data from said second bus segment, holding said data and transmitting said data to said third bus segment.

16. A method of segmented shared bus communication comprising:

providing first, second, third, and fourth first-level bus segments, first and second second-level bus segments, and a third-level bus segment;

providing a source chip and a destination chip;

providing first, second, third, and fourth first-level interface chips, said first first-level interface chip connecting said first first-level bus segment with said first second-level bus segment, said second first-level interface chip connecting said second first-level bus segment with said first second-level bus segment, said third first-level interface chip connecting said third first-level bus segment with said second second-level bus segment, said fourth first-level interface chip connecting said fourth first-level bus segment with said second second-level bus segment, said first first-level bus segment connecting said source chip with said first first-level interface chip, said fourth first-level bus segment connecting said destination chip with said fourth first-level interface chip;

providing first and second second-level interface chips for connecting said second and third first-level segments, respectively, with said third-level bus segment;

transmitting data from said source chip over said first first-level bus segment to said first first-level interface chip;

transmitting said data from said first first-level interface chip over said first second-level bus segment to said second first-level interface chip;

transmitting said data from said second first-level interface chip over said second first-level bus segment to said first second-level interface chip;

transmitting said data from said first second-level interface chip, over said third-level bus segment to said second second-level interface chip;

transmitting said data from said second second-level interface chip, over said third first-level bus segment to said third first-level interface chip;

transmitting said data from said third first-level interface chip, over said second second-level bus segment to said fourth first-level interface chip; and

transmitting said data from said fourth first-level interface chip, over said fourth first-level bus segment to said destination chip.

17. The method of claim 16, wherein:

the source chip, first first-level bus segment, and first first-level interface chip reside on a first multi-chip carrier;

the second first-level bus segment, second first-level interface chip and first second-level interface chip reside on a second multi-chip carrier;

the first second-level bus segment is a first board bus;

the first board bus, first and second multi-chip carriers reside on a first board;

the third first-level bus segment, third first-level interface chip and second second-level interface chip reside on a third multi-chip carrier;

the destination chip, fourth first-level bus segment, and fourth first-level interface chip reside on a fourth multi-chip carrier;

the second second-level bus segment is a second board bus;

the second board bus, third and fourth multi-chip carriers reside on a second board; and

the third-level bus segment is a backplane bus connecting the first and second boards.

18. A synchronous segmented shared bus for communication in a computer, the synchronous segmented shared bus comprising:

a plurality of bus segments including at least one lowest-level bus segment and at least one highest-level bus segment, each of said plurality of bus segments being connected for communication with at least one other bus segment, said plurality of bus segments connected to define a plurality of ordered bus levels wherein each bus segment can communicate with at least one other bus segment which is in an adjacent level;

a plurality of registers connected to said plurality of buses for holding data received from a bus before said data is sent to an adjacent-level bus segment;

wherein the voltage level used to represent a logic level on at least one bus segment is different from the voltage level used to represent the logic level on an adjacent-level bus segment.