Secondary cache system for portable computer

• US 5,632,038 A
• Filed: 02/22/1994
• Issued: 05/20/1997
• Est. Priority Date: 02/22/1994
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Fuller, Samuel
• Primary Examiner(s): Auve, Glenn A.
• Application Number:
  US08/199,915
• Time in Patent Office: 1,183 Days
• Field of Search: 395/750, 395/425, 395/470, 395/471, 395/472, 365/226, 365/227, 364/707
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A secondary cache memory system is disclosed for use in a portable computer that increases system performance while also conserving battery life. The secondary cache includes a cache controller for controlling the transfer to and from a cache memory, comprised of fast SRAM circuits. The cache controller includes a control and status register with at least three status bits to control power to the cache, and to insure that the data stored in the cache memory is coherent with system memory. A control and power management logic checks the contents of the control and status register, and monitors the activity level of the processor. When the processor is determined to be inactive, the control and power management logic turns off the cache by changing the state of a bit in the control and status register. Before doing so, however, the control and power management logic checks the status of a second bit in the control register to determine if some or all of the contents of the cache need to be flushed to system memory. During power up, the control and power management logic checks another status bit in the control register to determine if the contents of the cache is invalid, and if so, clears the cache.

Claims

1. A power management system for a portable computer, the power management system comprising:

a system memory for storing and accessing dam;

a processor that accesses data from the system memory and which transmits data to the system memory for storage;

a cache electrically connected to said processor and to said system memory for expediting the transfer of data between the processor and the system memory;

said cache including a cache controller and a cache memory;

wherein the cache controller includes a control register with a bit that is variable between a first and a second value and the value of the bit determines whether power is applied to the cache memory; and

control logic electrically connected to said cache for selectively providing power to said cache.

2. A system, as in claim 1, wherein the control logic turns off the cache when the processor is inactive.

3. A system as in claim 1, wherein the control logic turns on the cache when the processor is active.

4. A system as in claim 1, wherein the control logic turns on and turns off the cache by changing the bit value.

5. A system as in claim 4, wherein said cache memory implements a write back design, and said control register includes a second bit that indicates whether the data in the cache memory has been written back to said system memory.

6. A system as in claim 5, wherein the control logic, prior to turning off power to the cache memory, flushes the data stored in the cache memory to the system memory when the second bit indicates that data in the cache has not been written back to the system memory.

7. A system as in claim 5, wherein the control register includes a third bit that identifies whether data in the cache memory is valid.

8. A system as in claim 7, wherein the control logic clears invalid data in the cache when the third bit indicates that invalid data is present.

9. A power management system for a portable computer, wherein the portable computer includes a microprocessor with a central processor and an internal cache memory, the power management system comprising:

a secondary cache memory in said portable computer that is electrically connected to said processor for reducing the number of wait states encountered by the central processor;

control logic electrically connected to said central processing unit and to said secondary cache memory;

wherein said control logic monitors the activity of said central processor and turns off said secondary cache memory when the processor is inactive, while the processor remains operational.

10. A system as in claim 9, wherein the control logic turns on the secondary cache memory when the processor becomes active.

11. A system as in claim 10, wherein said secondary cache memory includes a control register with a bit that indicates whether the secondary cache includes write back lines.

12. A system as in claim 11, wherein the control logic checks the bit and flushes the secondary cache memory prior to turning off the secondary cache memory.

13. A power management system for a portable computer, wherein the portable computer includes a microprocessor with a central processor and an internal cache memory, the power management system comprising:

a secondary cache memory in said portable computer that is electrically connected to said processor for reducing the number of wait states encountered by the central processor;

control logic electrically connected to said central processing unit and to said secondary cache memory,

wherein said control logic monitors the activity of said central processor and turns off said secondary cache memory when the processor is inactive,

and wherein the control logic turns on the secondary cache memory when the number of wait states become excessive.

14. A system for conserving power in a portable computer, said portable computer including a processor and conventional memory, the system comprising:

a cache for expediting the transfer of data between the processor and the conventional memory, said cache including;

a cache controller with a control register that includes a first bit, a second bit and a third bit, each of said bits having two states; and

a cache memory comprised of SRAM circuits with a cache directory for storing addresses and a memory buffer with lines for storing data;

a control and power management logic connected to said cache controller, wherein said control and power management logic;

changes the state of the first bit to control power to the cache memory;

checks the state of the second bit to determine if lines in the cache memory must be flushed to conventional memory prior to turning off power to the cache; and

checks the state of the third bit to determine if data in said cache memory is valid after said cache is turned on.

15. A method for conserving power in a portable computer that includes a processor, a system memory and a secondary cache memory, comprising the steps of:

(a) turning on the secondary cache memory while maintaining the processor in an operational state;

(b) determining if the processor is inactive;

(c) turning off the secondary cache memory if the processor is inactive; and

(d) determining if the processor is active.

16. A method as in claim 15, further comprising the steps of:

(a)(1) determining if data in the secondary cache memory is valid; and

(a)(2) clearing the data from the secondary cache memory that is invalid.

17. A method as in claim 16, wherein step (a)(1) includes checking a status bit to determine if the data in the secondary cache memory is valid.

18. A method for conserving power in a portable computer that includes a processor, a system memory and a cache memory, comprising the steps of:

(a) turning on the cache memory by changing the state of a control bit;

(b) determining if the processor is inactive;

(c) turning off the cache memory by changing the state of the control bit if the processor is inactive; and

(d) determining if the processor is active.

19. A method as in claim 18, wherein step (c) includes the step of checking a status bit to determine whether the cache memory is a write back design that includes dirty lines.

20. A method as in claim 19, wherein the dirty lines are flushed to the system memory.