Method for detecting wafer defects

• US 5,633,173 A
• Filed: 07/13/1995
• Issued: 05/27/1997
• Est. Priority Date: 07/14/1994
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Bae, Sang M.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/502,178
• Time in Patent Office: 684 Days
• Field of Search: 430/311, 430/313, 430/314, 430/22, 430/30, 437/924, 437/7, 437/8
• US Class Current: 438/16
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/54466 Located in a dummy or reference die
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for detecting wafer defects, comprising the steps of: forming dummy dies useful as an alignment mark at edge portions of a flat wafer, the edge portions having no pattern die; loading the wafer in a defect detecting apparatus; arranging the edge portions of the dummy dies; inspecting the wafer for defects to give data for the defects; and carrying out subsequent processes, according to which the detected defects are utilized to inspect for process defects at subsequent process steps, which makes it easy to monitor organic relations between the wafer defects and the process defects and between the process defects themselves.

Claims

1. A method for detecting wafer defects, comprising the steps of:

forming dummy dies at edge portions of a flat wafer containing no pattern die;

performing a first step of inspecting defects on a surface of the wafer containing no pattern die;

determining the coordinates of the defects, using said dummy dies as reference marks;

performing a pattern die forming step;

performing a second step of inspecting defects on a surface of the wafer after said die forming step; and

comparing the defect coordinates and characteristics from said first and said second defect inspecting steps.

2. A method in accordance with claim 1, wherein said dummy dies are formed with rectangular protrusive or depressive photosensitive film patterns.

3. A method in accordance with claim 1, wherein two dummy dies are formed on said wafer.

4. A method in accordance with claim 1, wherein said dummy dies formed on said wafer are etched to a predetermined depth.

5. A method in accordance with claim 1, wherein said flat wafer is a bare wafer or film-deposited wafer having a smooth surface.