Multilayer wiring structure for attaining high-speed signal propagation

• US 5,633,479 A
• Filed: 07/25/1995
• Issued: 05/27/1997
• Est. Priority Date: 07/26/1994
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hirano, Naohiko
• Primary Examiner(s): Thomas, Laura
• Application Number:
  US08/506,518
• Time in Patent Office: 672 Days
• Field of Search: 361/805, 361/792, 361/793, 361/794, 361/795, 174/255, 174/262, 439/47, 439/74, 333/243, 333/1, 333/161, 333/246
• US Class Current: 174/255
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0224 Patterned shielding planes, ground planes or power planes H05K1/0253 takes precedence
• CPC Class Codes: H05K 1/0237 High frequency adaptations H05K1/0216 takes precedence
• CPC Class Codes: H05K 1/0253 Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings H05K1/0251 takes precedence
• CPC Class Codes: H05K 1/0289 having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/09663 Divided layout, i.e. conductors divided in two or more parts
• CPC Class Codes: H05K 2201/09681 Mesh conductors, e.g. as a ground plane

Abstract

Signal wiring layers are formed between a power supply layer and a ground layer, which have conductor patterns each constituted by a plurality of parallel strip-shaped conductors. The above layers are isolated from each other by insulating layers. The signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the power supply layer, and the signal wiring layer has wires which are arranged in parallel with the parallel strip-shaped conductors of the conductor pattern of the ground layer.

Claims

1. A multilayer wiring structure for use in a semiconductor device, comprising:

a potential supply layer including a plurality of parallel strip-shaped conductors, each of which has a predetermined potential; and

a signal wiring layer provided on said potential supply layer, with an insulating layer interposed therebetween, said signal wiring layer including wires which are arranged in parallel with the parallel strip-shaped conductors.

2. The multilayer wiring structure according to claim 1, further comprising:

another pair of a potential supply layer and a signal wiring layer which are identical to said potential supply layer and said signal wiring layer, and which have the same positional relationship with each other as that between said potential supply layer and said signal wiring layer; and

another insulating layer interposed said another pair of the potential supply layer and the signal wiring layer.

3. The multilayer wiring structure according to claim 1, wherein a width of each of the parallel strip-shaped conductors of said potential supply layer is equal to or less than twice a width of each of the wires of said signal wiring layer, and a pitch at which the parallel strip-shaped conductors are arranged is equal to or less than three times the width of said each of the wires.

4. The multilayer wiring structure according to claim 1, wherein a width of each of the parallel strip-shaped conductors of said potential supply layer is greater than a width of each of the wires of said signal wiring layer and is not greater than twice the width of said each of the wires, and a pitch at which the parallel strip-shaped conductors are arranged is greater than the width of said each of the wires and is not greater than three times the width of said each of the wires.

5. The multilayer wiring structure according to one of claims 3 and 4, wherein the wires of said signal wiring layer include at least one wire which is situated opposite to one of the parallel strip-shaped conductors and at least one wire which is situated opposite to a space between adjacent two of the parallel strip-shaped conductors.

6. The multilayer wiring structure according to claim 5, further comprising another potential supply layer which is identical to said potential supply layer, and via-holes which are formed in at least one of parallel strip-shaped conductors of said another potential supply layer at a pitch, which is equal to or less than twenty times a pitch at which the parallel strip-shaped conductors are arranged, such that the via-holes connect said potential supply layer and said another potential supply layer.

7. The multilayer wiring structure according to claim 6, wherein those parallel strip-shaped conductors of the parallel strip-shaped conductors which have a high potential and those parallel strip-shaped conductors of the parallel strip-shaped conductors which have a low potential are alternately arranged.

8. The multilayer wiring structure according to claim 1, wherein said insulating layer is formed of any one of resin material and ceramic material.

9. A multilayer wiring structure which is made up of a power supply/ground layer and a signal wiring layer situated just below or just above said power supply/ground layer, and on which a plurality of semiconductor elements are mounted, the multilayer wiring structure comprising:

a plurality of parallel strip-shaped conductors which are included in said power supply/ground layer;

a plurality of wires which are included in said signal wiring layer, and arranged in parallel with the parallel strip-shaped conductors of said power supply/ground layer; and

an insulating layer interposed between said power supply/ground layer and said signal wiring layer.

10. The multilayer wiring layer according to claim 9, further comprising:

another pair of a power supply/ground layer and a signal wiring layer which are identical to said power supply/ground layer and said signal wiring layer, and which have the same positional relationship with each other as that between said power supply/ground layer and said power supply/ground layer; and

another insulating layer interposed between said another pair of the power supply/ground layer and the signal wiring layer.

11. The multilayer wiring layer according to claim 9, wherein a width of each of the parallel strip-shaped conductors of said power supply/ground layer is equal to or less than twice a width of each of the wires of said signal wiring layer, and a pitch at which the parallel strip-shaped conductors are arranged is equal to or less than three times the width of said each of the wires.

12. The multilayer wiring layer according to claim 9, wherein a width of the parallel strip-shaped conductors of said power supply/ground layer is greater than a width of each of the wires of said signal wiring layer and is not greater than twice the width of said each of the wires, and a pitch at which the parallel strip-shaped conductors are arranged is greater than the width of said each of the wires and is not greater than three times the width of said each of the wires.

13. The multilayer wiring layer according to one of claims 11 and 12, further comprising:

at least one power supply/ground layer and at least one signal wiring layer, which are identical to said power supply/ground layer and said signal wiring layer, which have the same positional relationship with each other as that between said power supply/ground layer and said signal wiring layer, and which are arranged such that said signal wiring layer and said at least one wiring layer are situated between said power supply/ground layer and said at least one power supply/ground layer;

at least two insulating layers which are respectively interposed between said signal wiring layer and said at least one signal wiring layer, and said at least one signal wiring layer and said at least one power supply/ground layer; and

via-holes which are formed in at least one of the parallel strip-shaped conductors of each of said power supply/ground layer and said at least one power supply/ground layer at a pitch, which is equal to or less than twenty times the pitch at the parallel strip-shaped conductors which are arranged, such that the via-holes connect said power supply/ground layer and said at lease one power/ground layer.

14. The multilayer wiring structure according to claim 13, wherein the wires of said signal wiring layer includes:

at least one wire which is arranged opposite to one of the parallel strip-shaped conductors of said power supply/ground layer; and

at least one wire which is arranged opposite to a space between adjacent two of the parallel strip-shaped conductors of said power supply/ground layers, and the wires of said at least one signal wiring layer includes;

at least one wire which is arranged opposite to one of the parallel strip-shaped conductors of said at least one power supply/ground layer; and

at least one wire which is arranged opposite to a space between adjacent two of the parallel strip-shaped conductors of said at least one power supply/ground layer.

15. The multilayer wiring structure according to claim 13, wherein the parallel strip-shaped conductors of said each of said power supply/ground layer and said at least one power supply conductor layer are constituted by power supply conductors and ground conductors, the power supply conductors and the ground conductors being alternately arranged.