Battery pack having a processor controlled battery operating system

• US 5,633,573 A
• Filed: 11/10/1994
• Issued: 05/27/1997
• Est. Priority Date: 11/10/1994
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Duracell Incorporated (Berkshire Hathaway Incorporated)
• Inventors: Friel, Daniel D., Hull, Matthew P., Taylor, Alwyn H., Wieczorek, Rudi, van Phuoc, Duong, Zeising, Elmar, Hruska, Louis W.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): TOATLEY, GREGORY J
• Application Number:
  US08/336,945
• Time in Patent Office: 929 Days
• Field of Search: 320/5, 320/19, 320/20, 320/22, 320/30, 320/35, 320/48, 324/426, 365/96, 365/104
• US Class Current: 320/128
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
• CPC Class Codes: H01M 10/42 Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells H01M10/60 takes precedence
• CPC Class Codes: H01M 10/4257 Smart batteries, e.g. electronic circuits inside the housing of the cells or batteries
• CPC Class Codes: H01M 10/44 Methods for charging or discharging circuits for charging H02J7/00
• CPC Class Codes: H01M 10/48 Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte constructional details of current conducting connections for detecting conditions inside cells or batteries, e.g. details of voltage sensing terminals, H01M50/569
• CPC Class Codes: H01M 6/5011 for several cells simultaneously or successively
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02J 7/00036 Charger exchanging data with battery
• CPC Class Codes: H02J 7/00047 with provisions for charging different types of batteries
• CPC Class Codes: H02J 9/061 for DC powered loads
• CPC Class Codes: Y02E 60/10 Energy storage using batteries
• CPC Class Codes: Y10S 320/13 Fault detection

Abstract

A battery pack and a method of operating a battery system. The battery pack includes a rechargeable battery and a processor for monitoring the battery during charging and discharging. The processor receives data values representing the battery voltage, temperature and current, and the processor performs a series of calculations using those data values. The processor has normal, standby and sleep modes. In the normal mode, the processor performs the series of calculations at first regular cycles, and in the standby mode, the processor performs the series of calculations at second regular cycles, which are longer than the first cycles. Preferably, the processor enters the standby mode when the battery current falls below a predetermined current level, and the processor enters the sleep mode when the battery voltage falls below a first predetermined voltage level. Also, the processor exits the sleep mode when the battery voltage rises above a second predetermined voltage level higher than the first predetermined voltage level.

Claims

1. A smart battery having a power management system capable of self powered operation, even when nominally fully discharged, said smart battery comprising:

(a) a plurality of rechargeable cells connected to a pair of terminals to provide electrical power to an external device during a discharge mode and to receive electrical power during a charge mode, as provided or determined by said remote device;

(c) an analog means for generating analog signals representative of battery voltage, temperature and current at said terminals,

(d) a hybrid integrated circuit (IC) having an analog to digital convertor, a first clock and a microprocessor having a first algorithm for sampling the analog signals at a first period and converting them to digital signals representative of battery voltage, current and temperature;

a second algorithm for sampling the analog signals at predetermined intervals of said first period when battery current has dropped below a predetermined value; and

a third algorithm for disabling said analog to digital convertor, said first clock and said microprocessor when the battery voltage drops below a predetermined sleep mode value;

(e) a data memory defined within said hybrid IC for storing a plurality of calculated charge parameters, even when said battery is nominally fully discharged, said charge parameters including at least a learned full charge capacity and remaining capacity,

(f) a second clock means for initializing said first clock and said microprocessor during said first and said second algorithm, said clock means also initializing a comparator circuit for enabling a start signal for said microprocessor, said first clock and said analog to digital convertor whenever said battery voltage rises above a predetermined value.

2. A battery pack comprising:

terminal means for connecting the battery pack to a battery powered device;

a battery including at least one rechargeable battery cell connected to the terminal means, said battery having

i) a discharge mode for supplying electrical power to the battery powered device, and

ii) a charge mode for receiving electrical power from the terminal means;

means to sense and to generate signals representing battery voltage, battery temperature, and battery current;

a memory area for storing data values including at least values representing battery voltage, battery temperature and battery current; and

a processor for receiving the signals representing battery voltage, battery temperature and battery current, and for performing a predefined series of calculations using said signals;

wherein the processor has (i) a normal mode, (ii) a standby mode, and (iii) a sleep mode, and wherein

in the normal mode, the processor performs said series of calculations at first regular cycles, and

in the standby mode, the processor performs said series of calculations at second regular cycles, said second cycles being longer than said first cycles.

3. A battery pack according to claim 2, wherein:

the processor enters the standby mode when the battery current falls below a predetermined current level; and

the processor enters the sleep mode when the battery voltage falls below a first predetermined voltage level.

4. A battery pack according to claim 3, wherein the processor exits the sleep mode and enters the standby mode or the normal mode when the battery voltage rises above a second predetermined voltage level higher than the first predetermined voltage level.

5. A battery pack according to claim 4, wherein, the processor exits the sleep mode and enters the normal mode when the battery current is above the predetermined current level when the battery voltage rises above the second predetermined voltage level.

6. A battery pack according to claim 4, wherein, the processor exits the sleep mode and enters the standby mode when the battery current is below the predetermined current level when the battery voltage rises above the second predetermined voltage level.

7. A battery pack according to claim 2, wherein, in the sleep mode, the processor is essentially off.

8. A battery pack according to claim 2, wherein:

the means to sense and to generate signals includes

i) sensing means to sense and to generate analog signals representing battery voltage, battery temperature and battery current, and

ii) an analog to digital converter having abled and disabled states, wherein in the abled state, the converter receives said analog signals and converts said analog signals to digital signals representing battery voltage, battery temperature and battery current; and

in the sleep mode, the processor places the analog-to-digital converter in the disabled mode.

9. A battery pack according to claim 2, wherein the battery has a variable capacity, and said series of calculations includes calculating a value representing remaining capacity of the battery.

10. A battery pack according to claim 2, wherein:

the battery has a nominally fully discharged voltage value;

the memory area receives operating power from the battery and requires a minimum operating voltage to maintain said stored data values; and

said minimum operating voltage is below said nominally fully discharged voltage value, wherein the memory area maintains said stored data values even when the battery is nominally fully discharged.

11. A battery pack according to claim 2, wherein:

the length of each of the second cycles is an integer multiple of the length of each of the first cycles.

12. A battery pack according to claim 8, wherein the analog-to-digital converter, the processor, and the memory area receive operating power from the battery.

13. A battery pack according to claim 2, further including:

data receiving means to receive data from the battery powered device, said receiving means having an abled state and a disabled state;

in the abled state, the receiving means is able to receive data from the battery powered device; and

in the disabled state, the receiving means is disabled from receiving data from the battery powered device.

14. A battery pack according to claim 13, wherein:

each of the first cycles includes first and second intervals; and

during each of the first intervals of the first cycles, the processor (i) performs said series of calculations, and (ii) places the receiving means in the disabled state to inhibit the transmission of data to the processor from the battery powered device while the processor is performing said calculations.

15. A battery pack according to claim 2, wherein the processor performs additional calculations, said additional calculations including calculating a value representing a learned full charge capacity of the battery.

16. A battery pack according to claim 2, further comprising:

a comparator circuit connected to the sensing means to receive the signal representing battery voltage, and to generate a wake-up signal, and to transmit the wake-up signal to the processor, when the battery voltage is above the predetermined voltage level; and

wherein the processor enters the standby mode or the normal mode when the processor receives the wake-up signal from the comparator circuit.

17. A battery pack according to claim 8, further comprising a switching network connected to the sensing means and to the analog-to-digital converter, for receiving the analog signals from the sensing means and transmitting the analog signals, one at a time, to the analog-to-digital converter.

18. A battery pack comprising:

terminal means for connecting the battery pack to a battery powered device;

a battery including at least one rechargeable battery cell connected to the terminal means, said battery having

i) a discharge mode for supplying electrical power to the battery powered device, and

ii) a charge mode for receiving electrical power from the terminal means;

means to sense and to generate signals representing battery voltage, battery temperature, and battery current;

a memory area for storing data values including at least values representing battery voltage, battery temperature and battery current;

an internal oscillator for generating internal clock signals at a first frequency,

a processor for receiving the signals representing battery voltage, battery temperature and battery current, and for performing a predefined series of calculations using said signals;

wherein each of said calculations includes a series of timed steps, and the timing of said steps is controlled by the clock signals from the internal oscillator;

an external oscillator for generating clock signals at a second frequency; and

means connecting the external oscillator to the processor to transmit signals from the external oscillator to the internal oscillator;

wherein the processor performs said series of calculations at regular cycles, each of said cycles being started by receipt by the processor of one of the clock signals from the external oscillator.

19. A battery pack according to claim 18, wherein:

the processor has normal and standby modes;

in the normal mode, the processor performs said series of calculations at first regular cycles, and in the standby mode, the processor performs said series of calculations at second regular cycles; and

each of the first and second cycles is started by receipt of the processor of one of the clock signals from the external oscillator.

20. A battery pack according to claim 18, wherein:

the processor has normal and sleep modes;

in the normal mode, the processor performs said series of calculations;

in the sleep mode, the processor does not perform said series of calculations;

the battery pack further includes a comparator circuit connected to the sensing means to receive the analog signal representing battery voltage, and connected to the external oscillator to receive the clock signals therefrom;

when the comparator circuit receives the clock signals from the external oscillator, the comparator circuit generates a wake-up signal and transmits the wake-up signal to the processor, if the battery voltage is above a predetermined level; and

the processor enters the normal mode when the processor receives the wake-up signal from the comparator circuit.

21. A battery pack according to claim 19, further including data receiving means to receive data from the battery powered device, said receiving means having an abled state and a disabled state;

in the abled state, the receiving means is able to receive data from the battery powered device; and

in the disabled state, the receiving means is disabled from receiving data from the battery powered device;

each of the said regular cycles includes first and second intervals; and

during each of the first intervals of said regular cycles, the processor (i) performs said series of calculations, and (ii) places the receiving means in the disabled state to inhibit the transmission of data to the processor from the battery powered device while the processor is performing said calculations.

22. A battery pack comprising:

terminal means for connecting the battery pack to a battery powered device;

a battery including at least one rechargeable battery cell connected to the terminal means, said battery having

i) a discharge mode for supplying electrical power to the battery powered device, and

ii) a charge mode for receiving electrical power from the terminal means;

means to sense and to generate signals representing battery voltage, battery temperature, and battery current;

a memory area for storing data values including at least values representing battery voltage, battery temperature and battery current;

an internal oscillator for generating internal clock signals at a first frequency,

a processor for receiving the signals representing battery voltage, battery temperature and battery current, and for performing a predefined series of calculations using said signals;

wherein each of said calculations includes a series of timed steps, and the timing of said steps is controlled by the clock signals from the internal oscillator;

an external oscillator for generating clock signals at a second frequency; and

means connecting the external oscillator to the processor to transmit to the processor the clock signals from the external oscillator; and

wherein the processor has (1) a normal mode and (ii) a standby mode,

in the normal mode, the processor performs said series of calculations at first regular cycles, each of said first cycles being started by receipt by the processor of one of the clock signals from the external processor, and

in the standby mode, the processor performs said series of calculations at second regular cycles, said second cycles being longer than said first cycles, each of said second cycles also being started by receipt by the processor of one of the clock signals form the external processor.

23. A battery pack according to 22, wherein:

the processor enters the standby mode when the battery current falls below a predetermined current level; and

the processor further includes a sleep mode and enters the sleep mode when the battery voltage falls below a first predetermined level.

24. A battery pack according to 22, wherein the processor exits the sleep mode and enters the standby mode or the normal mode when the battery voltage rises above a second predetermined voltage level higher than the first predetermined voltage level.

25. A battery pack according to claim 24, further including:

a comparator circuit connected to the sensing means to receive the signal representing battery voltage, and to generate a wake-up signal, and to transmit the wake-up signal to the processor, when the battery voltage is above a predetermined level; and

wherein the processor enters the normal mode or the standby mode when the processor receives the wake-up signal from the comparator circuit.

26. A battery pack according to claim 22, wherein:

the means to sense and to generate signals includes

i) sensing means to sense and to generate analog signals representing battery voltage, battery temperature and battery current, and

ii) an analog-to-digital converter having abled and disabled states, wherein in the abled state, the converter receives said analog signals and converts said analog signals to digital signals representing battery voltage, battery temperature and battery current; and

the battery pack further comprises a switching network connected to the sensing means and the analog-to-digital converter for receiving the analog signals from the sensing means and transmitting the analog signals, one at a time, to the analog-to-digital converter.

27. A battery pack according to claim 22, further including data receiving means to receive data from the battery powered device, and wherein:

said receiving means has an abled state and a disabled state;

in the abled state, the receiving means is able to receive data from the battery powered device;

in the disabled state, the receiving means is disabled from receiving data from the battery powered device;

each of the first cycles includes first and second intervals; and

during each of the first intervals of the first cycles, the processor (i) performs said series of calculations, and (ii) places the receiving means in the disabled state to inhibit the transmission of data to the processor from the battery powered device while the processor is performing said calculations.

28. A method of operating a battery system having a rechargeable battery and a processor, the method comprising:

sensing, generating and storing signals representing, battery voltage, battery temperature and battery current;

the processor repeatedly performing a series of predefined calculations using said signals;

wherein the processor has (i) a normal mode and (ii) a standby mode;

in the normal mode, the processor performs said series of predefined calculations at first regular cycles; and

in the standby mode, the processor performs said series of predefined calculations at second regular cycles.

29. A method according to claim 28, wherein:

the processor enters the standby mode when the battery current falls below a predetermined current level; and

the processor further includes a sleep mode and enters the sleep mode when the battery voltage falls below a first predetermined voltage level.

30. A method according to claim 29, wherein the processor exits the sleep mode and enters the standby mode or the normal mode when the battery voltage rises above a second predetermined voltage level higher than the first predetermined voltage level.

31. A method according to claim 28, wherein:

the step of sensing, and generating signals representing battery voltage, battery temperature and battery current includes the steps of

i) sensing and generating analog signals representing battery voltage, battery temperature and battery current and

ii) converting said analog signals to digital data values representing battery voltage, battery temperature and battery current; and

the converting step includes the step of transmitting said analog signals, one at a time, to an analog-to-digital converter to convert said analog signals to said digital data values.

32. A method according to claim 31, wherein the analog-to-digital converter has (i) an abled state to convert said analog signals to said digital signals, and (ii) a disabled state, and the method further includes the step of placing the analog-to-digital converter in the disabled state when the battery voltage falls below a predetermined voltage level.

33. A method according to claim 30, the steps of:

comparing the battery voltage to the second predetermined voltage level at predefined intervals;

generating a wake-up signal when the battery voltage is above said second predetermined voltage level;

transmitting the wake-up signal to the processor; and

wherein the processor enters the normal mode or the standby mode in response to transmitting the wake-up signal to the processor.

34. A method according to claim 28, wherein each of the first cycles has first and second intervals and the battery system further includes a data receiving means, and wherein:

the step of performing the predefined calculations includes the step of performing the predefined calculations in the first interval of each of the first cycles; and

the method further includes the steps of

i) transmitting data to the data receiving means, and

ii) disabling the data receiving means during the first interval of each of the first cycles to inhibit the transmission of data to the data receiving means while the processor is performing the predefined calculations.

35. A method of operating a battery system having a rechargeable battery, a processor, and first and second oscillators for generating clock signals at first and second frequencies, the method comprising:

sensing, generating and storing signals representing battery voltage, battery temperature and battery current;

repeatedly performing a series of predefined sequential calculations;

starting each of said repeated series of sequential calculations in response to a clock signal from the first oscillator; and

controlling the timing of the timed steps of the sequential calculations using the clock signals from the second oscillator.

36. A method according to claim 35, wherein:

the processor has normal and standby modes;

the step of performing the series of predefined calculations includes the steps of

i) performing said series of calculations at first regular cycles when the processor is in the normal mode, and

ii) performing said series of calculations at second regular cycles when the processor is in the standby mode; and

the step of starting each of said regular cycles includes the step of starting each of said first regular cycles and each of said second regular cycles in response to transmission to the processor of one of the clock signals from the first oscillator.

37. A method according to claim 35, wherein the step of converting the analog signals representing battery voltage, battery temperature and battery current to digital signals includes the steps of transmitting said analog signals, one at a time, to an analog-to-digital converter to convert said analog signals to said digital signals.

38. A method according to claim 35, wherein:

the processor has normal and sleep modes;

in the normal mode, the processor performs said series of calculations;

in the sleep mode, the processor does not perform said series of calculations; and

the method includes the further step of the processor entering the normal mode when the battery voltage is above a predetermined voltage level.

39. A method according to claim 38, wherein the step of the processor entering the normal mode includes the steps of:

comparing the battery voltage to the predetermined voltage level at predefined intervals;

generating a wake-up signal when the battery voltage is above said predetermined voltage level;

transmitting the wake-up signal to the processor; and

the processor entering the normal mode in response to transmitting the wake-up signal to the processor.

40. A method according to claim 39, wherein the battery system further includes a voltage comparator, and wherein:

the comparing step includes the steps of transmitting the clock signals from the first oscillator to the voltage comparator to activate the voltage comparator at said defined intervals to compare the battery voltage to the predetermined voltage level; and

the generating step includes the step of the voltage comparator generating the wake-up signal when the battery voltage is above the predetermined voltage level.

41. A method according to claim 35, wherein:

the processor has normal and sleep modes;

in the normal mode, the processor performs said series of calculations;

in the sleep mode, the processor does not perform said series of calculations;

the method further includes the steps of

i) the processor entering the sleep mode when the battery voltage falls below a preset voltage level, and

ii) disabling the second oscillator when the processor enters the sleep mode to inhibit the second oscillator from generating clock signals when the battery voltage falls below the preset voltage level.

42. A method according to claim 35, further including the step of the processor performing additional calculations at predefined times, said additional calculations including calculating a value representing a learned full charge capacity of the battery.

43. A method of operating a battery system having a rechargeable battery, a processor, and first and second oscillators for generating clock signals at first and second frequencies, the method comprising:

sensing, generating and storing analog signals representing battery voltage, battery temperature and battery current;

repeatedly performing a series of predefined calculations;

controlling the timing of the sequential calculations using the clock signals from the first oscillator;

wherein the processor has (i) a normal mode, (ii) a standby mode, and (iii) a sleep mode;

in the normal mode, the processor performs said series of predefined calculations at first regular cycles; and

in the standby mode, the processor performs said series of predefined calculations at second regular cycles

transmitting the clock signals from the second oscillator to the processor;

starting each of the first and second cycles in response to transmission to the processor of one of the clock signals from the second oscillator.

44. A method according to claim 43 further including the steps of the processor (i) entering the standby mode when the battery current falls below a preset current level, (ii) entering the sleep mode when the battery voltage falls below a first preset voltage level, and (iii) exiting the sleep mode and entering the normal mode or the standby mode when the battery voltage is above a second predetermined voltage level higher than the first predetermined level.

45. A method according to claim 44, wherein the step of the processor entering the normal mode or the standby mode includes the steps of:

comparing the battery voltage to the second predetermined voltage level at predefined intervals;

generating a wake-up signal when the battery voltage is above said second predetermined voltage level;

transmitting the wake-up signal to the processor; and

the processor entering the normal mode or the standby mode in response to transmitting the wake-up signal to the processor.

46. A method according to claim 45, wherein the battery system further includes a voltage comparator, and wherein:

the comparing step includes the steps of transmitting the clock signals from the second oscillator to the voltage comparator to activate the voltage comparator at said defined intervals to compare the battery voltage to the predetermined voltage level; and

the step of generating the wake up signal includes the step of the voltage comparator generating the wake-up signal when the battery voltage is above the second predetermined voltage level.

47. A method according to claim 44, wherein:

the step of entering the sleep mode includes the step of disabling the first oscillator when the processor enters the sleep modes to inhibit the first oscillator from generating clock signals when the battery voltage falls below the first preset voltage level.

48. A method according to claim 43, wherein the battery has a variable capacity, and said predefined calculations include calculating a value representing remaining battery capacity of the battery.