Monolithic microwave integrated circuit apparatus

• US 5,633,610 A
• Filed: 09/29/1995
• Issued: 05/27/1997
• Est. Priority Date: 01/08/1993
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Maekawa, Itaru, Tanaka, Kuninobu, Ohgihara, Takahiro
• Primary Examiner(s): Cunningham, Terry
• Application Number:
  US08/536,245
• Time in Patent Office: 606 Days
• Field of Search: 327/91, 327/94, 327/124, 327/307, 327/339, 327/355, 327/361, 327/362, 327/430, 327/431
• US Class Current: 327/355
• CPC Class Codes: H03D 7/125 with field effect transistors
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 3/1935 with junction-FET devices
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence

Abstract

A monolithic microwave semiconductor integrated circuit including a bias stabilizing circuit of a current mirror type formed of a bias control transistor formed of an enhancement mode compound semiconductor field effect transistor and a biased transistor formed of an enhancement mode compound semiconductor field effect transistor.

Claims

1. A microwave semiconductor integrated circuit, comprising:

a mixer circuit formed of an active circuit element field effect transistor having its source-drain path connected between an RF input and IF output, a first resistor connected at an RF input side of the source-drain path to ground and a second resistor connected between an IF output side of the source-drain path to ground, and a gate of the mixing circuit connecting to a local oscillator as an input; and

a bias circuit comprising an enhancement mode field effect transistor having its source directly connected to ground, its gate connecting through a third resistor to the gate of the mixer circuit field effect transistor, the gate also connecting directly to the drain of the bias circuit field effect transistor, and a fourth resistor connecting the drain of the bias circuit field effect transistor to a power supply potential.

2. A circuit according to claim 1 wherein a first capacitor connects between the mixer circuit field effect transistor and the RF input, a second capacitor is connected between the IF output and the mixer circuit field effect transistor, a third capacitor is connected between the gate of the mixer circuit field effect transistor and the local oscillator input, and a fourth capacitor is connected between the gate of the bias circuit field effect transistor and ground.