Binary-to-ternary encoder

• US 5,633,631 A
• Filed: 06/27/1994
• Issued: 05/27/1997
• Est. Priority Date: 06/27/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Teckman, Timothy A.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US08/266,149
• Time in Patent Office: 1,065 Days
• Field of Search: 341/57, 341/58, 341/95, 341/106, 341/59
• US Class Current: 341/58
• CPC Class Codes: H03M 5/16 the pulses having three levels
• CPC Class Codes: H03M 7/06 the radix thereof being a positive integer different from two
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes

Abstract

A method for encoding binary data for transmission over a serial link as a ternary code. Binary data is received and mapped into a binary code. The binary code is translated into a ternary code, and the ternary code is transmitted over the serial link. The ternary code is selectively inverted according to a predetermined protocol such that the serial link maintains a time-averaged zero DC balance.

Claims

1. A method for encoding binary data for transmission as ternary data over a serial link, the method comprising the steps of:

receiving binary data;

mapping the binary data into a binary code;

determining whether the ternary code is positive balanced;

determining whether the serial link has a positive direct current (DC) balance, by checking a state register, wherein the state register indicates that the serial link has the positive DC balance when the state register is in a first state, if the ternary code is positive balanced;

inverting the binary code if the serial link has the positive DC balance and the ternary code is positive balanced; and

translating the binary code into the ternary code.

2. The method of claim 1, wherein the step of determining whether the ternary code is positive balanced comprises the step of:

checking a value of the binary data, wherein the binary code for the binary data is positive balanced if the value of the binary data is less than a predetermined value and the least significant bit is in a predetermined state.

3. The method of claim 2, wherein the predetermined value is 245 and the predetermined state is logic high.

4. The method of claim 1, wherein the first state is logic high.

5. The method of claim 1, wherein the step of inverting the ternary code comprises the step of inverting the binary code before the binary code is translated into the ternary code.

6. The method of claim 1, wherein the binary data comprises eight bits.

7. The method of claim 6, wherein the binary code comprises twelve bits.

8. The method of claim 7, wherein the ternary code comprises six ternary symbols.

9. The method of claim 8, wherein the step of translating the binary code into a ternary code comprises the steps of translating each two bit group of the binary code into a single ternary symbol.

10. A method for encoding binary data for transmission as ternary data over a serial link, the method comprising the steps of:

receiving binary data;

mapping the binary data into a binary code;

determining whether a ternary code is negative balanced;

determining whether the serial link has a negative direct current (DC) balance, by checking a state register, wherein the state register indicates that the serial link has the negative DC balance when the state register is in a first state, if the ternary code is negative balanced;

inverting the binary code if the serial link has the negative DC balance and the ternary code is negative balanced; and

translating the binary code into the ternary code.

11. The method of claim 10, wherein the first state is logic high.

12. A method for decoding a ternary code received from a serial link into binary data, the method comprising the steps of:

receiving the ternary code;

translating the ternary code into a binary code;

determining whether the ternary code is zero balanced;

mapping the binary code into binary data if the ternary code is zero balanced;

determining whether the ternary code is positive balanced;

determining whether the serial link has a zero DC balance by checking a state register, a first state of the state register indicating the zero DC balance for the serial link, if the ternary code is positive balanced;

mapping the binary code into binary data if the ternary code is positive balanced and the serial link has the zero DC balance;

determining whether the ternary code is negative balanced;

determining whether the serial link has a positive DC balance if the ternary code is negative balanced;

inverting the binary code if the serial link has the positive DC balance and the ternary code is negative balanced; and

,

mapping the binary code into binary data after inverting the binary code if the serial link does has a positive DC balance and the ternary code is negative balanced.

13. The method of claim 12, the method further comprising the step of signaling an error if the ternary code is positive balanced and the serial link has the positive DC balance.

14. The method of claim 13, the method further comprising the step of signaling an error if the ternary code is negative balanced and the serial link has the zero DC balance.

15. The method of claim 14, wherein the positive balanced is positive one balanced, and negative balanced is negative one balanced.

16. The method of claim 15, the method further comprising the step of signaling the error if the ternary code is not zero balanced, positive one balanced, or negative one balanced.

17. The method of claim 12, wherein the first state of the state register is a logic low.

18. A binary-to-ternary encoder for encoding binary data for transmission of as a ternary code over a serial link, the binary-to-ternary encoder comprising:

a mapping circuit coupled to receive the binary data, the mapping circuit for mapping the binary data to a binary code;

a plurality of programmable inverters coupled to the mapping circuit for selectively inverting the binary code in response to an active control signal;

encode control circuitry coupled to receive the binary data, the encode control circuitry including a state register for maintaining a state of the serial link, wherein the encode control circuitry enables the plurality of programmable inverters to invert positive balanced binary codes when the state register indicates that a positive binary code has been transmitted, the encode control circuitry for providing the active control signal if the binary code is positive balanced and the serial link has a positive direct current (DC) balance; and

a binary-to-ternary translator coupled to receive the binary code, the binary-to-ternary translator for translating the binary code into the ternary codes.

19. The binary-to-ternary data encoder of claim 18, wherein the plurality of programmable inverters act do not invert the binary code when the control signal is inactive.

20. The binary-to-ternary encoder of claim 18, wherein the control signal is active high and each of the plurality of programmable inverters is an XOR gate having the control signal as one input.

21. The binary-to-ternary encoder of claim 18, wherein the control signal is active low and each of the plurality of programmable inverters is an XNOR gate having the control signal as one input.

22. The binary-to-ternary encoder of claim 18, wherein each of the plurality of programmable inverters includes a buffer and driver, the buffer and the driver being coupled to receive the control signal such that only one of the buffer and the driver is enabled to output a portion of the binary code.

23. The binary-to-ternary encoder of claim 18, wherein the mapping circuit comprises combinational logic.

24. The binary-to-ternary encoder of claim 18, wherein mapping circuit comprises a look-up table.

25. The binary-to-ternary encoder of claim 18, wherein the binary-to-ternary translator comprises:

an OR gate coupled to receive a first bit of a binary code and a second bit of the binary code;

an AND gate coupled to receive the first bit and the second bit;

a digital to analog converter (DAC) coupled to receive outputs of the OR and AND gates;

a level shifter coupled to receive an output of the DAC, the level shifter for generating ternary voltage levels in response to the output of the DAC.

26. A ternary-to-binary decoder for decoding ternary data received from a serial link into binary data, the ternary-to-binary decoder comprising:

a ternary-to-binary translator coupled to the serial link, the ternary-to-binary translator for translating a ternary code into a binary code;

a mapping circuit coupled to the ternary-to-binary translator, the mapping circuit for mapping the binary code into binary data; and

decode control circuitry coupled to the ternary-to-binary translator, the decode control circuitry including a state register for indicating a state of the serial link, the state register being set to a first state if a previously received binary code was positive balanced, the decode control circuitry providing the active control signal if the binary code is positive balanced and the state register is in the first state, the decode control circuitry for providing the active control signal if the binary code is positive balanced and a previously received binary code was positive balanced.

27. The ternary-to-binary decoder of claim 26, wherein the ternary-to-binary decoder further comprises

a plurality of programmable inverters coupled between the ternary-to-binary translator and the mapping circuit, the plurality of programmable inverters for inverting the binary code in response to an active control signal.

28. A computer network comprising:

a serial link for transmitting ternary data;

a first node coupled to the serial link, the first node including a first circuit that operates using binary data and a binary-to-ternary encoder for encoding binary data received from the first circuit for transmission of a ternary code over the serial link, wherein the binary-to-ternary data encoder comprises;

a mapping circuit coupled to receive the binary data, the mapping circuit for mapping the binary data to a binary code;

a plurality of programmable inverters coupled to the mapping circuit for selectively inverting the binary code in response to an active control signal;

encode control circuitry coupled to receive the binary data, the encode control circuitry including a state register for maintaining a state of the serial link, wherein the encode control circuitry enables the plurality of programmable inverters to invert positive balanced binary codes when the state register indicates that a positive binary code has been transmitted, the encode control circuitry for providing the active control signal if the binary code is positive balanced and the serial link has a positive direct current (DC) balance; and

a binary-to-ternary translator coupled to receive the binary code, the binary-to-ternary translator for translating the binary code into the ternary code;

a second node coupled to the serial link, the second node including a second circuit that operates using the binary data and a ternary-to-binary decoder for decoding ternary codes received from the serial link into binary data for the second circuit.

29. The computer network of claim 28, wherein the plurality of programmable inverters do not invert the binary code when the control signal is inactive.

30. The computer network of claim 28, wherein each of the plurality of programmable inverters includes a buffer and an inverter, the buffer and the inverter being coupled such that only one of the buffer and the inverter is enabled to output a portion of the binary code.

31. The computer network of claim 28, wherein the control signal is active high and each of the plurality of programmable inverters is an XOR gate having the control signal as one input.

32. The computer network of claim 28, wherein the control signal is active low and each of the plurality of programmable inverters is an XNOR gate having the control signal as one input.

33. The computer network of claim 28, wherein the mapping circuit comprises combinational logic.

34. The computer network of claim 28, wherein mapping circuit comprises a look-up table.

35. The computer network of claim 28, wherein the binary-to-ternary translator comprises:

an OR gate coupled to receive a first bit of a binary code and a second bit of the binary code;

an AND gate coupled to receive the first bit and the second bit;

a digital to analog converter (DAC) coupled to receive outputs of the OR and AND gates;

a level shifter coupled to receive an output of the DAC, the level shifter for generating ternary voltage levels in response to the output of the DAC.

36. The computer network of claim 28, wherein the ternary-to-binary decoder comprises:

a ternary-to-binary translator coupled to the serial link, the ternary-to-binary translator for translating the ternary code into the binary code;

a second mapping circuit coupled to the ternary-to-binary translator, the second mapping circuit for mapping the binary code into binary data.

37. The ternary-to-binary decoder of claim 36, wherein the ternary-to-binary decoder further comprises:

a second plurality of programmable inverters coupled between the ternary-to-binary translator and the second mapping circuit, the second plurality of programmable inverters for inverting the binary code in response to an active control signal;

decode control circuitry coupled to the ternary-to-binary translator and the second plurality of programmable inverters, the decode control circuitry for providing the active control signal if the binary code is positive balanced and a previously received binary code was positive balanced.

38. The ternary-to-binary decoder of claim 37, wherein the decode control circuitry includes a second state register for indicating a state of the serial link, the second state register being set to a first state if a previously received binary code was positive balanced, the decode control circuitry providing the active control signal if the binary code is positive balanced and the state register is in the first state.