Electrostatic discharge protection device

• US 5,633,780 A
• Filed: 04/18/1996
• Issued: 05/27/1997
• Est. Priority Date: 12/21/1994
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Polaroid Corporation (PLR IP Holdings LLC)
• Inventors: Cronin, David V.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): Medley, Sally C.
• Application Number:
  US08/634,170
• Time in Patent Office: 404 Days
• Field of Search: 361/56, 361/91, 361/111, 361/212, 361/220, 206/706, 206/707
• US Class Current: 361/220
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 13/0084 Containers and magazines for components, e.g. tube-like magazines

Abstract

An electrostatic discharge protection device is disclosed which automatically connects selected connector pins of a semiconductor chip package ("SCP") or connectors on printed circuit boards such that the connector pins are held at a common voltage until insertion of the SCP into a receptor or until insertion of a cable into the connector which overcomes an internal resilient bias of the electrostatic discharge protection device causing the common connection to be removed. Removal of the SCP from the receptor or the cable from its connector removes the force which overcomes the bias, thereby reestablishing the common electrical connection thus automatically moving the electrostatic discharge protection device between inoperative and operative positions.

Claims

1. A method for fabricating an electrostatic discharge protection device for use with a semiconductor chip package of a type having a top surface and an opposite bottom surface and a plurality of lateral surfaces integral with said top and bottom surfaces where the semiconductor chip package has extending therefrom a plurality of connector pins disposed in a spaced apart relationship with respect to each other for insertion into a mating receptacle, said method comprising

stamping a base to form a plurality of apertures corresponding to the plurality of connector pins such that the at least one row of connector pins pass through the plurality of apertures and to form one or more cuts in the base transverse to the central axis of the base such that an area surrounding each of the plurality of apertures is free to move at an angle relative to a plane of the base;

depositing a conductive material on said base to provide electrical communication between outer portions of the plurality of apertures; and

shaping said base to have a resilient bias to urge the outer portions of the plurality of apertures into contact with the connector pins such that the electrostatic discharge protection device has an operative position for connecting a shunt across selected pins of the connector pins and has an inoperative position for disconnecting said shunt to provide electrical isolation between the connector pins where insertion of said semiconductor chip package into said mating receptacle moves the base into the inoperative position by overcoming the inward bias and removal of the semiconductor chip package from the mating receptacle automatically moves the base into said operative position.

2. The method according to claim 1 wherein said step of depositing comprises a step of coating a conductive ink onto said base.

3. The method according to claim 1 wherein said step of depositing further comprises a step of applying the conductive material in excess over the outer portions of the plurality of apertures to ensure mechanical contact with the connector pins.

4. The method according to claim 3 wherein said step of depositing further comprises a step of photo-etching the conductive material to form the apertures.

5. The method according to claim 3 wherein said step of depositing further comprises a step of mechanically punching the conductive material to form the apertures.

6. The method according to claim 1 wherein said step of depositing comprises a step of laminating a conductive material onto said base.