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Fault simulation of testing for board circuit failures

  • US 5,633,812 A
  • Filed: 09/29/1992
  • Issued: 05/27/1997
  • Est. Priority Date: 09/29/1992
  • Status: Expired due to Fees
First Claim
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1. A method of simulating detection of faults in a digital circuit comprising the steps of:

  • defining a logical probe for nets to be measured, for conditions to be satisfied before a measurement of the nets can be made, and for providing a duration of a time-limited measurement window during which said measurement takes place;

    simulating operation of the circuit for fault-free and faulty operation;

    monitoring for a satisfaction of the defined conditions to be satisfied before measurement can be made;

    measuring net values for the nets to be measured upon the satisfaction of the defined conditions during fault-free and faulty operation of the circuit; and

    recording a fault-free value and a list of faults which can be detected.

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