Formatter

• US 5,633,815 A
• Filed: 06/07/1995
• Issued: 05/27/1997
• Est. Priority Date: 08/14/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Young, William R.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US08/478,683
• Time in Patent Office: 720 Days
• Field of Search: 364/715.03, 364/745, 364/748
• US Class Current: 708/204
• CPC Class Codes: H03D 7/165 at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0021 Decimation, i.e. data rate reduction techniques H04B1/0025 takes precedence
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04J 1/05 using digital techniques
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

A digital down converter with a programmable mixing down frequency and a programmable extraction bandwidth uses a Read Only Memory, ROM, based sin/cos generator plus a programmable high decimation filter followed by a gain compensating scaling multiplier and a Finite Impulse Response, FIR, filter. Output format options are also programmable, and programming commands are serially loaded into registers. Various components may be isolated for efficient testing and also subsystem operation.

Claims

1. A formatter for serially formatting digital data, comprising:

an N bit most significant bit (MSB) to least significant bit (LSB) shifting shift register for receiving N bit input data, the shift register having a serial input;

a serial two'"'"'s complementer operatively connected to the shift register for receiving the LSB first data from the shift register wherein the complementer performs two'"'"'s complementatic, n on the data, and alternatively passing the data without two'"'"'s complementing the data;

a serial rounder operatively connected to the output of the two'"'"'s complementer wherein said rounder is selectably programmed to add 1 to the serial data, and alternatively passing the data without modifying the data, the serial rounder having an output connected to the serial input of the shift register;

a zero detector operatively connected to the shift register for detecting data equal to 0, wherein if the data is equal to 0 during a floating point conversion then all data bits are forced to zero else, the data is unaffected by the zero detector;

an exponent counter circuit operatively connected to the output of the serial rounder to compute an exponent in a floating point representation; and

a detection means operatively connected to said shift register for detecting the most positive two'"'"'s complement number and forcing the resulting data to be the most positive number.

2. The formatter of claim 1 wherein said shift register further comprises means for outputting data MSB or LSB first.

3. The formatter of claim 1 wherein N is 38.

4. The formatter of claim 1 further comprising a clock control wherein all conversion operations are accomplished within a 64 clock cycle period.

5. The formatter of claim 1 wherein the input data into the serial shift register is in two'"'"'s complement format.

6. The formatter of claim 1 wherein the floating point format is the IEEE Single Precision Floating Point Format and the length of magnitude of the IEEE format is 24.

7. A method of formatting an input digital data signal having a number of bits into formatted output data comprising the steps of:

(a) storing an input digital data signal in a storing means as stored input data;

(b) selecting a predetermined number of output data bits;

(c) converting the stored input data to a selected arithmetic representation, the selected arithmetic representation consisting of an arithmetic representation from the group comprising two'"'"'s complement, unsigned, signed magnitude and floating point representation;

(d) selectively two complementing stored input data during conversion from two'"'"'s complement data to sign magnitude or floating point data and outputting converted data;

(e) selectively rounding converted data when the number of output data bits is less than the number of input data bits, and outputting rounded data; and

(f) saturation limiting during the selectively rounding of the converted data.

8. The method as in claim 7 wherein the conversions are performed serially from least significant bit to most significant bit format.

9. The method as claimed in claim 7 further comprising the step of selectively outputting the output data as serial output in least significant bit (LSB) format or a most significant bit (MSB) format.

10. The method as claimed in claim 7 further comprising the step of complementing the most significant bit of the data which is to be converted to obtain a conversion between the two'"'"'s complement data and the unsigned format data.

11. The method as in claim 7 wherein the step of rounding comprises the steps of:

adding a 1 to the bit position one less significant bit than the selected rounded bit position of the data to be converted; and

truncating bits of the data to be converted less than the selected rounded bit position.

12. The method as in claim 7 wherein the step of saturation limiting comprises the step of detecting that a number to be rounded is the most positive number and forcing the result of the rounding to be the most positive number.

13. The method of claim 7 wherein the step of converting from two'"'"'s complement data to sign magnitude data representation comprises the steps of:

setting the sign bit of the sign magnitude data equal to the MSB of the two'"'"'s complement data;

setting the magnitude of the sign magnitude data equal to the two'"'"'s complement data when the MSB of the two'"'"'s complement data is equal to 0; and

setting the magnitude of the sign magnitude data equal to the two'"'"'s complement of the two'"'"'s complement data when the MSB of the two'"'"'s complement data is equal to 1.

14. The method of claim 7 wherein the step of converting from two'"'"'s complement data to floating point data comprises the steps of:

detecting that all of the bits of the two'"'"'s complement data more significant than n least significant bits of the two'"'"'s complement data are equal, wherein n is equal to the number of bits of the floating point mantissa;

converting the two'"'"'s complement data to sign magnitude;

rounding the magnitude data to a floating point magnitude length if all of the data bits more significant than a least significant bit length of the data bits of the two'"'"'s complement data were detected as not all equal, otherwise inhibiting the rounding of the magnitude data;

computing the exponent of the sign magnitude data; and

detecting that the two'"'"'s complement data being converted to floating point representation is all zeros and forcing the final floating representation to be equal to zero.

15. The method of claim 14 wherein the step of computing the exponent comprises the steps of:

examining current bits of the magnitude of the sign magnitude data LSB to MSB;

loading a counter with the maximum expected value that the exponent can have after normalization;

reloading the counter with the maximum expected value each time the current bit of the magnitude data equals 1;

decrementing the counter by 1 each time the current bit of the magnitude data is equal to 0;

wherein the counter will contain the exponent when the MSB of the magnitude data is processed; and

circular shifting data to discard the most significant 1 in the magnitude data and to align the magnitude data in the correct bit position.

16. The method of claim 7, wherein the selected number of output bits are one of 16, 24, 32 and 38.