Random number generator with wait control circuitry to enhance randomness of numbers read therefrom

• US 5,633,816 A
• Filed: 09/01/1995
• Issued: 05/27/1997
• Est. Priority Date: 09/01/1995
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Wallace, William C.
• Primary Examiner(s): Gordon, Paul P.
• Assistant Examiner(s): PATEL, RAMESH B
• Application Number:
  US08/523,002
• Time in Patent Office: 634 Days
• Field of Search: 364/717, 364/717.15, 364/715.08, 395/182.02, 395/457, 342/51
• US Class Current: 708/252
• CPC Class Codes: G06F 2207/581 Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
• CPC Class Codes: G06F 2207/583 Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register

Abstract

A random number generator circuit for generating a sequence of random numbers. A linear feedback shift register includes shift register circuitry that holds a plurality of shift register bits. The shift register circuitry shifts the shift register bits responsive to a periodic system clock signal, shifting out one of the shift register bits while shifting in a feedback bit whose value is provided at a feedback input of the shift register. Tap circuitry generates the feedback bit by logically combining selected ones of the shift register bits. Sampling circuitry provides at least a portion of the shift register bits as one of the sequence of random numbers. Interface circuitry provides a random number from the shift register, to a processor via a processor bus, in response to a processor request signal being asserted. Significantly, the interface circuitry includes wait control circuitry that receives the asserted processor request signal and that inserts wait states onto the processor bus if the asserted processor request signal occurs less than a minimum number of periods of the system clock signal from a previous asserted processor request signal. Preferably, the "minimum number of periods" is determined from a register which is programmable by the processor. Thus, the randomness of the sequence produced by the linear feedback shift register is enhanced in those situations where the processor requests random numbers close together in time.

Claims

1. A random number generator system for generating a sequence of random numbers, comprising:

a linear feedback shift register, that includes

shift register circuitry that holds a plurality of shift register bits and that, responsive to transitions of a periodic system clock signal, shifts said shift register bits, shifting out one of said shift register bits while shifting in a feedback bit whose value is provided at a feedback input of the shift register;

tap circuitry that generates the feedback bit; and

sampling circuitry that provides at least a portion of said shift register bits as one of said sequence of random numbers; and

interface circuitry that provides said one of said sequence of random numbers to a processor in response to a processor request signal being asserted, wherein the processor request signal is for requesting the sampling circuitry to provide a random number, said interface circuitry including wait control circuitry that receives said asserted processor request signal and that inserts wait states onto the processor bus if the asserted processor request signal occurs less than a minimum number of periods of the system clock signal from a previous asserted processor request signal.

2. The random number generator circuit of claim 1, and further comprising a programmable count register, wherein said minimum number of periods of the system clock signal is determined from a value in said programmable count register.

3. A random number generator system for generating a sequence of random numbers, comprising:

number generator circuitry that generates numbers, in sequence, responsive to transitions of a periodic system clock signal, the number generator circuitry including sampling circuitry that provides one of the generated numbers as one of said sequence of random numbers; and

interface circuitry that provides said one of said sequence of random numbers to a processor in response to a processor request signal being asserted, wherein the processor request signal is for requesting the sampling circuitry to provide a random number, said interface circuitry including wait control circuitry that receives said asserted processor request signal and that inserts wait states onto the processor bus if the asserted processor request signal occurs less than a minimum number of periods of the system clock signal from a previous asserted processor request signal.