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Random number generator with wait control circuitry to enhance randomness of numbers read therefrom

  • US 5,633,816 A
  • Filed: 09/01/1995
  • Issued: 05/27/1997
  • Est. Priority Date: 09/01/1995
  • Status: Expired due to Term
First Claim
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1. A random number generator system for generating a sequence of random numbers, comprising:

  • a linear feedback shift register, that includesshift register circuitry that holds a plurality of shift register bits and that, responsive to transitions of a periodic system clock signal, shifts said shift register bits, shifting out one of said shift register bits while shifting in a feedback bit whose value is provided at a feedback input of the shift register;

    tap circuitry that generates the feedback bit; and

    sampling circuitry that provides at least a portion of said shift register bits as one of said sequence of random numbers; and

    interface circuitry that provides said one of said sequence of random numbers to a processor in response to a processor request signal being asserted, wherein the processor request signal is for requesting the sampling circuitry to provide a random number, said interface circuitry including wait control circuitry that receives said asserted processor request signal and that inserts wait states onto the processor bus if the asserted processor request signal occurs less than a minimum number of periods of the system clock signal from a previous asserted processor request signal.

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