Serial access memory device capable of controlling order of access to memory cell areas

• US 5,633,829 A
• Filed: 07/31/1991
• Issued: 05/27/1997
• Est. Priority Date: 03/09/1990
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshimoto, Masahiko, Matsumura, Tetsuya
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/739,786
• Time in Patent Office: 2,127 Days
• Field of Search: 365/78, 365/189.05, 365/221, 365/230.08, 365/240
• US Class Current: 365/221
• CPC Class Codes: G06F 7/785 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting circuit are each comprised of ring pointers with a controllable number of stages. The number of stages of the ring pointers is controlled in response to control signals stored in a serial interface circuit. As a result, two ring pointers each having two stages are formed in the writing column selecting circuit while one ring pointer having four stages is formed in the reading column selecting circuit. After two data signals are written in selected two memory cell columns in parallel, written data signals are read out from serially selected four memory cell columns at a speed twice that in the writing. This serial access memory device is applied to a progressive scan conversion circuit for video signal processing.

Claims

1. A serial access memory device, comprising:

a memory cell array having a plurality of separately accessible memory cell areas;

each said area having memory cells disposed therein to store data signals;

a plurality of access means respectively connected to corresponding memory cell areas for accessing data signals stored in memory cells of said respective memory cell areas;

a plurality of activating means each connected to a corresponding one of said plurality of access means and responsive to a clock signal for activating said corresponding one of said plurality of access means; and

select signal storing means for storing a selecting signal and generating a plurality of control signals determined by said selecting signal;

each said activating means comprising selective coupling means responsive to said control signals generated by said select signal storing means for selectively coupling at least two of said plurality of activating means in a predetermined configuration selected for successively activating at least two corresponding access means in response to said clock signal.

2. The serial access memory device according to claim 1, wherein

said plurality of memory cell areas comprise a plurality of separately accessible memory cell columns.

3. The serial access memory device according to claim 1, wherein

said plurality of activating means are arranged to provide a ring pointer means operative in response to said clock signal.

4. The serial access memory device according to claim 2, wherein

said plurality of access means comprise a plurality of writing means each respectively connected to a corresponding one of said memory cell columns for writing data signals into the memory cells of said corresponding memory cell column.

5. The serial access memory device according to claim 2, wherein

said plurality of access means comprise a plurality of reading means each respectively connected to a corresponding one of said memory cell columns for reading stored data signals from the memory cells of said corresponding memory cell column.

6. The serial access memory device according to claim 4, wherein

said memory cell array comprises a plurality of bit lines each connected to memory cells of one of said plurality of memory cell columns to transmit data signals of the memory cells of said corresponding memory cell column, and

said plurality of writing means comprise a plurality of bit-line driving means each respectively connected to a corresponding one of said plurality of bit lines for driving the corresponding bit line in response to the data signals to be written in the memory cells of said corresponding memory cell column.

7. The serial access memory device according to claim 5, wherein

said memory cell array comprises a plurality of bit lines each connected to memory cells of one of said plurality of memory cell columns to transmit data signals of the memory cells of said corresponding memory cell column, and

said plurality of reading means comprise a plurality of amplifying means each respectively connected to a corresponding one of said plurality of bit lines to amplify data signals on the corresponding bit line read from the memory cells of said corresponding memory cell column.

8. The serial access memory device according to claim 1, wherein

said select signal storing means comprises shift register means responsive to an externally applied second clock signal for holding an externally applied selecting signal.

9. The serial access memory device according to claim 3, wherein

each of said plurality of activating means comprises cascaded master latch means and slave latch means which are operative in response to the clock signal.

17. The serial access memory device according to claim 1, wherein said plurality of activating means are arranged to provide a ring pointer,

each said activating means comprising programmable flip flop means.

18. The serial access memory device according to claim 17, wherein said ring pointer comprises a sequence of programmable flip flop means, each said programmable flip flop means comprises:

first input means for receiving a forward signal from a preceding programmable flip flop in said ring pointer;

first output means for providing a forward signal to a subsequent programmable flip flop in said ring pointer;

second input means for receiving a returning signal from said subsequent programmable flip flop;

second output means for providing a returning signal to said preceding programmable flip flop; and

path selecting means responsive to said control signals generated by said select signal storing means for establishing a connection path between a selected one of said first and second input means and a selected one of said first and second output means,

whereby a plurality of said programmable flip flop means are connected in a ring pointer means wherein a data bit circulates in accordance with said first clock signal.

19. The serial access memory device according to claim 18, wherein each said programmable flip flop means further comprises additional output means for providing an output signal to activate said corresponding one of said plurality of access means,

whereby programmed sequences of said access means are successively activated in accordance with a sequence of said programmable flip flops formed into said ring pointer means in accordance with said control signals generated by said select signal storing means.

10. A serial access memory device for converting first and second digital video data for progressive scan, comprising:

a memory cell array having four memory cell columns each having n memory cells disposed in k rows, where n and k are integers greater than one;

four writing means each respectively connected to a corresponding one of said four memory cell columns for writing one of the first or second video data in memory cells of said corresponding memory cell column;

first selecting means responsive to an externally applied first clock signal for alternately selecting a predetermined two of said four writing means;

said writing means selected by said first selecting means writing said first video data into memory cells of at least a first corresponding memory cell column;

second selecting means responsive to said externally applied first clock signal for alternately selecting the remaining two of said four writing means;

said writing means selected by said second selecting means writing said second video data into memory cells of at least a second corresponding memory cell column;

four reading means each respectively connected to a corresponding one of said four memory cell columns for reading stored data from memory cells therein; and

third selecting means responsive to an externally applied second clock signal for successively selecting individual ones of said four reading means,

said second clock signal having a frequency twice that of said first clock signal, and

said reading means selected by said third selecting means respectively reading data stored in the memory cells of said memory cell column corresponding thereto.

11. The serial access memory device according to claim 10, wherein

said first selecting means comprises first ring pointer means having two stages, said first ring pointer means responsive to the first clock signal for operation,

said second selecting means comprises second ring pointer means having two stages, said second ring pointer means responsive to the first clock signal for operation, and

said third selecting means comprises third ring pointer means having four stages, said third ring pointer means responsive to the second clock signal for operation.

12. The serial access memory device according to claim 10, wherein

the first digital video data comprise NTSC video data,

the second digital video data comprise line interpolating data,

n equals 8, and

k equals 455.

13. A serial access memory device for delaying at least first and second serial data, comprising:

a memory cell array having m memory cell columns each having n memory cells disposed in k rows, where m, n and k are integers greater than one;

m writing means each respectively connected to a corresponding one of said m memory cell columns for writing one of the first or second serial data in memory cells of said corresponding memory cell column;

first serial selecting means responsive to an externally applied first clock signal for successively selecting a predetermined i out of said m writing means, where i is an integer,

said i writing means selected by said first serial selecting means each respectively writing said one of said first and second serial data into memory cells of a memory cell column corresponding thereto;

second serial selecting means responsive to said first clock signal for successively selecting i out of the remaining (m-i) of said m writing means,

said i writing means selected by said second serial selecting means each respectively writing the other of said first and second serial data into memory cells of a memory cell column corresponding thereto;

m reading means each respectively connected to a corresponding one of said m memory cell columns for reading stored data from memory cells in said corresponding memory cell column;

third serial selecting means synchronized with said first serial selecting means for successively selecting corresponding i reading means,

said i reading means selected by said third serial selecting means each respectively reading stored data from memory cells of the memory cell column corresponding thereto; and

fourth serial selecting means synchronized with said second serial selecting means for successively selecting corresponding i reading means,

said reading means selected by said fourth serial selecting means each respectively reading stored data from memory cells of the memory cell column corresponding thereto.

14. The serial access memory device according to claim 13, wherein

said at least first and second serial data comprise a digital R signal, a digital D signal and a digital B signal contained in video signals.

15. The serial access memory device according to claim 14, further comprising:

a line memory for delaying said three digital signals on horizontal scanning lines.

16. The serial access memory device according to claim 15, wherein

said video signals are NTSC standard video signals,

i equals 2,

k equals 455,

m equals 6, and

n equals 8.

20. A serial access memory device, comprising:

a memory cell array having a plurality of separately accessible memory cell areas;

each said area having memory cells disposed therein to store data signals;

a plurality of access means each respectively connected to a corresponding one of said plurality of memory cell areas for accessing memory cells in said corresponding one of said plurality of memory cell areas;

a plurality of activating means each respectively connected to a corresponding one of said plurality of access means and responsive to a clock signal for activating said corresponding one of said plurality of access means; and

select signal storing means for storing a selecting signal and generating a plurality of control signals determined by said selecting signal;

said activating means comprising selective coupling means responsive to said control signals generated by said select signal storing means for selectively coupling said plurality of activating means in predetermined circuit configurations.

21. A serial access memory device comprising:

a memory array having a plurality of separately accessible memory cell areas, each said area having a plurality of memory cells and bit lines connected to said plurality of memory cells;

a plurality of data lines;

a plurality of access means respectively connected between respective bit lines of a corresponding memory cell area and a corresponding data line for transferring data between said corresponding data line and said respective bit lines of said corresponding memory cell area;

a plurality of activating means each responsive to a clock signal for generating an activating signal for activating a corresponding one of said plurality of access means; and

select signal generating means for generating a plurality of control signals;

wherein

each said activating means comprises_I

first and second input terminals,

first and second output terminals,

an activating signal generating means for generating said activating signal, said activating signal generating means having an input node and an output node, and

path selecting means for selecting one of said input terminals and one of said output terminals to form a path for transfer of said activating signal between connected ones of said activating means,

said path selecting means comprising first and second switching means;

said first switching means responsive to at least one of said plurality of control signals for connecting an input node of said activating signal generating means to a selected one of said first and second input terminals; and

said second switching means responsive to at least one of said plurality of control signals for connecting an output node of said activating signal generating means to a selected one of said first and second output terminals, whereby said activating signal is selectively transferred from a selected input terminal through said activating signal generating means to a selected output terminal.

22. A serial access memory device according to claim 21, wherein said path selecting means further comprises third switching means responsive to at least one of said plurality of control signals for connecting said input node to said output node through said first and second switching means.

23. A serial access memory device according to claim 21 wherein said path selecting means further comprises third switching means responsive to at least one of said plurality of control signals for connecting the input node to the output node of said activating signal generating means.

24. A serial access memory device according to claim 23 wherein said path selecting means further comprises a fourth switching means cooperating with said third switching means for connecting at least one of said input terminals to at least one of said output terminals and for bypassing the input and output nodes of said activating signal generating means.