Reduced area word line driving circuit for random access memory

• US 5,633,832 A
• Filed: 09/26/1995
• Issued: 05/27/1997
• Est. Priority Date: 09/26/1995
• Status: Expired due to Term

• Current Assignee: Smart Memory Solutions LLC (Acacia Research Corporation)
• Original Assignee: Alliance Semiconductor Corporation
• Inventors: Patel, Vipul C., Poteet, Kenneth A., Reddy, Chitranjan N.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/533,755
• Time in Patent Office: 609 Days
• Field of Search: 365/189.11, 365/230.06, 365/230.03
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12). The channel width of the inverter NMOS transistors (N2) are relatively large in relation to the inverter PMOS transistors (P2), allowing the NMOS transistors (N2) to be turned on by a voltage of Vcc-Vtn, where Vtn is the threshold voltage of the transfer transistors (N0).

Claims

1. In a semiconductor memory device having a first power supply voltage, a second power supply voltage, and a boost power supply voltage greater than the first power supply voltage, a word line driving circuit, comprising:

a decoder circuit including a select circuit having a number of active devices coupled between a decode node and the second power supply, the select circuit pulling the control node to the second power supply in response to a plurality of active decoder signals in a select operation, the decoder circuit further including a deselect circuit coupled between the first power supply and the control node, the deselect circuit pulling the control node to the first power supply in response to an active reset signal in a deselect operation; and

a plurality of word line driver stages, each said stage including,

a transfer transistor coupled between the decode node and a control node and responsive to word line select signal, the transfer transistor coupling the first power supply voltage to its respective control node in the deselect operation,

a first driver transistor of a first conductivity type having its source coupled to the boost voltage, its drain coupled to a word line, and its gate coupled to a control node,

a second driver transistor of a second conductivity type having its source coupled to the second power supply voltage, its drain coupled to the word line, and its gate coupled the control node, and

a level shifting transistor of the first conductivity type having its source coupled to the boost voltage, its drain coupled to the control node, and its gate coupled to the word line.

2. The word line driving circuit of claim 1 wherein:

the channel width of said level shifter transistor is small relative to the active devices of said decoder circuit, said decoder circuit overpowering said level shifting transistor and turning on the second driver transistor when said decoder circuit pulls the control node to the second power supply.

3. The word line driving circuit of claim 1 including:

a pull-up circuit for pulling the decode node to the first power supply voltage.

4. The word line driving circuit of claim 1 wherein:

the transfer transistors are of the second conductivity type.

5. The word line driving circuit of claim 4 wherein:

the transfer transistors are turned on by the first power supply being applied to their gates, the transfer transistors providing the first power supply voltage less their threshold voltage to their respective control nodes when the transfer transistors are turned on and the first power supply voltage is at the decode node, and

the channel width of the second driver transistors are large with respect to the channel widths of the first driver transistors, such that the second driver transistors are turned on by a control node voltage of the first power supply voltage less the threshold voltage of the transfer transistors.

6. The word line driving circuit of claim 4 wherein:

the transfer transistors are turned on by transfer signal applied to their gates, the transfer signal having at least a first portion at the boost power supply voltage.

7. The word line driving circuit of claim 4 including:

a pull-up circuit for pulling the decode node to the boost power supply voltage.

8. The word line driving circuit of claim 4 wherein:

the first driver transistor is a PMOS transistor having a first channel width; and

the second driver transistor is an NMOS transistor having a channel width that is greater than one half the first channel width.

9. The word line driving circuit of claim 8 wherein

the channel width of the second driver transistor is greater than the first channel width.

10. The word line driver circuit of claim 1 wherein:

the first power supply is a positive power supply;

the boost voltage is a positive voltage greater than the positive power supply; and

the first conductivity type is a p-channel type MOS transistor.

11. The word line driving circuit of claim 1 wherein:

the first driver transitors and the level shifter transistors are MOS transistors having a source, a drain, and a body, the bodies of said first driver transistors and level shifter transistors being coupled to the sources of their respective transistors.

12. The word line driving circuit of claim 11 wherein:

the first driver trasistor and the control node transistor share a common CMOS well.

13. The word line driving circuit of claim 1 wherein:

said decoder circuit includes a plurality of decoder transistors of the second conductivity type connected in series between the decode node and the second power supply, the gates of the decoder transistors each receiving a particular decoder address signal.

14. The word line driving circuit of claim 1 wherein:

during a read or write operation to a word line, the transfer transistor associated with the word line is turned on, and the transfer transistors not associated with the word line are turned off.

15. In a random access memory having a plurality of word lines, a word line driving circuit, comprising:

a driver circuit for each word line, said driver circuit including

a CMOS inverter having a first node coupled to a boost voltage, a second node coupled to a second supply voltage, a common gate forming a control node, and an output coupled to its respective word line,

a level shifter transistor of a first conductivity type having a source coupled to the boost voltage, a drain coupled to the control node, and a gate coupled to the word line;

a decoupling transistor for each driver circuit, each said decoupling transistor having a source connected to the control node of its respective driver circuit, the drains of said decoupling transistors being connected to a common decode node, a selected decoupling transistor coupling its respective control node to the common decode node in a select operation, each said decoupling transistor coupling its respective control node to the common decode node in a deselect operation; and

a decoder circuit intermediate the decode node and the second supply voltage, said decoder circuit coupling the decode node to the second supply voltage via at least one active device in response to a decoder address in the select operation, said decoder circuit coupling the decode node to a first power supply voltage in the deselect operation.

16. The word line driving circuit of claim 15 wherein:

the channel widths of the decoupling transistors and the active devices of said decoder circuit are more than half to the channel width of the level shifter transistors.

17. The word line driver circuit of claim 15 including:

pull-up means for pulling the decode node to a first supply voltage;

the coupling signal for said decoupling transistors is at the first supply voltage level such that the voltage at its respective control node is the first supply voltage less the threshold voltage of the decoupling transistor; and

the CMOS inverter drives its respective word line to the second supply voltage in response to a voltage at its input that is less than or equal to the first supply voltage less the threshold voltage of the decoupling transistors.

18. The word line driver circuit of claim 15 wherein:

the second supply voltage is ground;

the first supply voltage is a positive power supply;

the boost voltage is a positive voltage greater than that of the positive power supply; and

the relative channel width-to-length ratios (W/L) between the p-channel device and the n-channel device of each CMOS inverter is less than two.

19. The word line driver circuit of claim 15 wherein:

the second supply voltage is ground;

the first supply voltage is a positive power supply voltage;

the boost voltage is a positive voltage greater than the positive power supply;

the level shifter transistors are p-channel devices;

said decoupling transistors are n-channel devices; and

the active devices of said decoder circuit are n-channel transistors;

wherein

the smallest of the decoupling transistors of the decoder circuit transistors has a width-to-length ratios (W/L) that is at least three times that of the level shifter transistors.

20. The word line driving circuit of claim 15 including:

pull-up means for pulling the decode node to the boost voltage.

21. The word line driving circuit of claim 15 wherein:

at least a portion of the coupling signal is at the boost voltage.